DS32EL0421
- 5-bit DDR LVDS Parallel Data Interface
- Programmable Transmit De-emphasis
- Configurable Output Levels (VOD)
- Selectable DC-balanced Encoder
- Selectable Data Scrambler
- Remote Sense for Automatic Detection and Negotiation of Link Status
- On Chip LC VCOs
- Redundant Serial Output (ELX device only)
- Data Valid Signaling to Assist with Synchronization of Multiple Receivers
- Supports AC- and DC-coupled Signaling
- Integrated CML and LVDS Terminations
- Configurable PLL Loop Bandwidth
- Programmable Output Termination (50Ω or 75Ω).
- Built-in Test Pattern Generator
- Loss of Lock and Error Reporting
- Configurable via SMBus
- 48-pin WQFN Package with Exposed DAP
Key Specifications
- 1.25 to 3.125 Gbps Serial Data Rate
- 125 to 312.5 MHz DDR Parallel Clock
- -40° to +85°C Temperature Range
- >8 kV ESD (HBM) Protection
- Low Intrinsic Jitter — 35ps at 3.125 Gbps
All trademarks are the property of their respective owners.
The DS32EL0421/DS32ELX0421 is a 125 MHz to 312.5 MHz (DDR) serializer for high-speed serial transmission over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly interface.
The DS32EL0421/DS32ELX0421 serializes up to 5 parallel input LVDS channels to create a maximum data payload of 3.125 Gbps. If the integrated DC-balance encoding is enabled, the maximum data payload achievable is 2.5 Gbps.
The DS32EL0421/DS32ELX0421 serializers feature remote sense capability to automatically detect and negotiate link status with its companion DS32EL0124/DS32ELX0124 deserializers without requiring an additional feedback path.
The parallel LVDS interface reduces FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces.
The DS32EL0421/DS32ELX0421 is programmable through a SMBus interface as well as through control pins.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | DS32EL0421/ELX0421 125 - 312.5 MHz FPGA-Link Serializer w/ DDR LVDS Parallel I/F 数据表 (Rev. F) | 2013-4-15 | |||
| 应用手册 | LVDS Timing DS32ELX0421 and DS32ELX0124 Serializers and Deserializers (Rev. A) | 2013-4-26 | ||||
| 应用手册 | Expanding the Payload w/FPGA-Link DS32ELX0421 and DS32ELX0124 SER/DES (Rev. A) | 2013-4-26 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| WQFN (RHS) | 48 | Ultra Librarian |
订购和质量
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