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DS125BR800A

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具有输入 CTLE 和输出去加重功能的 12.5Gbps 8 通道转接驱动器

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DS125BR800A

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产品详情

Type Redriver Protocols General purpose, PCIe1, PCIe2, PCIe3, SAS1, SAS2, SAS3, SATA1, SATA2, SATA3 Applications 10G-KR, PCIe, SAS, SATA Number of channels 8 Speed (max) (Gbpp) 12.5 Supply voltage (V) 2.5, 3.3 Rating Catalog Operating temperature range (°C) -40 to 85
Type Redriver Protocols General purpose, PCIe1, PCIe2, PCIe3, SAS1, SAS2, SAS3, SATA1, SATA2, SATA3 Applications 10G-KR, PCIe, SAS, SATA Number of channels 8 Speed (max) (Gbpp) 12.5 Supply voltage (V) 2.5, 3.3 Rating Catalog Operating temperature range (°C) -40 to 85
WQFN (NJY) 54 55 mm² 10 x 5.5
  • Proven System Interoperability
  • Comprehensive multi-protocol Repeater Family
  • Low 65-mW/Channel (Typ) Power Consumption,
    With Option to Power Down Unused Channels
  • Transparent Management of Link Training
    Protocol for PCIe and SAS
  • Advanced Signal Conditioning Features
    • Rx CTLE up to 30 dB (24 dB for SAS3)
    • Tx De-Emphasis up to –12 dB
    • Tx Output Voltage Control: 700 – 1300 mV
  • Device Configuration Interface:
    • Pin Selection, EEPROM, or SMBus Interface
  • Single Supply Voltage: 2.5 V or 3.3 V
  • −40°C to 85°C Operating Temperature Range
  • 3-kV HBM ESDRating
  • Flow-Thru Pinout: 54-Pin LLP
    (10 mm × 5.5 mm, 0.5 mm pitch)
  • Supported Protocols
    • SAS/SATA
    • PCIe
    • Other Proprietary Interface up to 12.5 Gbps

All trademarks are the property of their respective owners.
  • Proven System Interoperability
  • Comprehensive multi-protocol Repeater Family
  • Low 65-mW/Channel (Typ) Power Consumption,
    With Option to Power Down Unused Channels
  • Transparent Management of Link Training
    Protocol for PCIe and SAS
  • Advanced Signal Conditioning Features
    • Rx CTLE up to 30 dB (24 dB for SAS3)
    • Tx De-Emphasis up to –12 dB
    • Tx Output Voltage Control: 700 – 1300 mV
  • Device Configuration Interface:
    • Pin Selection, EEPROM, or SMBus Interface
  • Single Supply Voltage: 2.5 V or 3.3 V
  • −40°C to 85°C Operating Temperature Range
  • 3-kV HBM ESDRating
  • Flow-Thru Pinout: 54-Pin LLP
    (10 mm × 5.5 mm, 0.5 mm pitch)
  • Supported Protocols
    • SAS/SATA
    • PCIe
    • Other Proprietary Interface up to 12.5 Gbps

All trademarks are the property of their respective owners.

The DS125BR800A is an extremely low-power high-performance multi-protocol repeater/redriver designed to support eight channels of PCIe, SAS, and other high-speed interface serial protocols up to 12.5 Gbps. The receiver's continuous time linear equalizer (CTLE) provides a boost of up to +30 dB at 6.25 GHz (12.5 Gbps) in each of its eight channels and is capable of opening an input eye that is completely closed due to inter symbol interference (ISI) induced by interconnect medium such as 30in+ backplane traces or 8m+ copper cables, hence enabling host controllers to ensure an error free end-to-end link. The strong linear equalization maximizes interconnect channel extension when the DS125BR800A is placed with the majority of channel loss on the devices input side. Adjustable transmit de-emphasis and output voltage amplitude help to compensate for the remaining channel attenuation on the output side.

When operating in SAS-3 and PCIe Gen-3 mode, the DS125BR800A transparently allows the host controller and the end point to optimize the full link and negotiate transmit equalizer coefficients. This seamless management of the link training protocol ensures system level interoperability with minimum latency. With a low power consumption of 65 mW/channel (typ) and option to turn-off unused channels, the DS125BR800A enables energy efficient system design. A single supply of 3.3 V or 2.5 V is required to power the device.

The programmable settings can be applied easily via pins, software (SMBus or I2C) or loaded via an external EEPROM. When operating in the EEPROM mode, the configuration information is automatically loaded on power up, which eliminates the need for an external microprocessor or software driver.

The DS125BR800A is an extremely low-power high-performance multi-protocol repeater/redriver designed to support eight channels of PCIe, SAS, and other high-speed interface serial protocols up to 12.5 Gbps. The receiver's continuous time linear equalizer (CTLE) provides a boost of up to +30 dB at 6.25 GHz (12.5 Gbps) in each of its eight channels and is capable of opening an input eye that is completely closed due to inter symbol interference (ISI) induced by interconnect medium such as 30in+ backplane traces or 8m+ copper cables, hence enabling host controllers to ensure an error free end-to-end link. The strong linear equalization maximizes interconnect channel extension when the DS125BR800A is placed with the majority of channel loss on the devices input side. Adjustable transmit de-emphasis and output voltage amplitude help to compensate for the remaining channel attenuation on the output side.

When operating in SAS-3 and PCIe Gen-3 mode, the DS125BR800A transparently allows the host controller and the end point to optimize the full link and negotiate transmit equalizer coefficients. This seamless management of the link training protocol ensures system level interoperability with minimum latency. With a low power consumption of 65 mW/channel (typ) and option to turn-off unused channels, the DS125BR800A enables energy efficient system design. A single supply of 3.3 V or 2.5 V is required to power the device.

The programmable settings can be applied easily via pins, software (SMBus or I2C) or loaded via an external EEPROM. When operating in the EEPROM mode, the configuration information is automatically loaded on power up, which eliminates the need for an external microprocessor or software driver.
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* 数据表 DS125BR800A Low-Power 12.5-Gbps 8-Channel (Unidirectional) Repeater With Input E 数据表 2013年 11月 5日
应用手册 利用适用于 10G 至 12.5G 应用的以太网转接驱动器和重定时器来扩大覆盖范围 (Rev. A) PDF | HTML 英语版 (Rev.A) 2023年 2月 12日
技术文章 Differential pairs: how an equalizer solves insertion-loss impairment PDF | HTML 2016年 1月 12日
应用手册 Understanding EEPROM Programming for High Speed Repeaters and Mux Buffers 2014年 10月 9日

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