DS110DF1610
- Pin-Compatible Family
- DS150DF1610: 12.5 - 15G
- DS125DF1610: 9.8 to 12.5G
- DS110DF1610: 8.5 – 11.3G
- 4x4 Analog Cross Point Switch for Each Quad
- Fully-Adaptive CTLE
- Self-Tuning DFE, With Optional Continuous Adaption
- On-Chip, AC-coupling on Receive Inputs
- Adjustable Transmit VOD
- Adjustable 3-Tap Transmit FIR Filter
- Locks to Half/Quarter/Eighth Data Rates For Legacy Support
- On-Chip Eye Monitor (EOM), PRBS Checker, PRBS Pattern Generator
- Supports IEEE 1149.1 and 1149.6
- Programmable Output Polarity Inversion
- Input Signal Detection, CDR Lock Detection
- Single 2.5-V ±5% Power Supply
- SMBus-Based Register Configuration
- Optional EEPROM Configuration
- 15-mm × 15-mm, 196-Pin FCBGA Package
- Operating Temp Range : –10°C to +85°C
The DS110DF1610 is a sixteen-channel multi-rate retimer with integrated signal conditioning. The device includes a full adaptive Continuous Time Linear Equalizer (CTLE), Decision Feedback Equalizer (DFE), clock and data recovery (CDR), and a transmit FIR filter to enhance the reach and robustness over long, lossy, crosstalk impaired high speed serial links to achieve BER < 1×10-15.
Each channel of the DS110DF1610 independently locks to serial data at 8.5 to 11.3 Gbps and any supported sub-multiple. A simple external oscillator (±100ppm) that is synchronous or asynchronous with the incoming data stream can be used as a reference clock to speed up the lock process. Integrated 4x4 cross point switches allow for full non-blocking routing or broadcasting within each quad of the DS110DF1610.
Programmable transmit FIR filter offers control of the pre-cursor, main tap and post-cursor for transmit equalization. The fully adaptive receive equalization (CTLE and DFE) enables longer distance transmission in lossy copper interconnects and backplanes with multiple connectors.
A non-disruptive mission mode eye-monitor feature allows link monitoring internal to the receiver. The built-in PRBS generator and checker compliment the internal diagnostic features to complete standalone BERT measurements. Built-in JTAG enables manufacturing tests.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | DS110DF1610 8.5- to 11.3-Gbps 16-Channel Retimer 数据表 (Rev. A) | PDF | HTML | 2017-6-15 | ||
| 应用手册 | 利用适用于 10G 至 12.5G 应用的以太网转接驱动器和重定时器来扩大覆盖范围 (Rev. A) | PDF | HTML | 英语版 (Rev.A) | 2023-2-12 | ||
| 模拟设计期刊 | Green box testing: A method for optimizing high-speed serial links | 2016-7-21 | ||||
| 应用手册 | Understanding EEPROM Programming for 10G to 12.5G Retimers | PDF | HTML | 2016-1-13 |
设计与开发
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| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| FCBGA (ABB) | 196 | Ultra Librarian |