DP83TG721S-Q1
- IEEE802.3bp 1000BASE-T1 compliant
- OA TC10 compliant, <20µA sleep current
- Local and remote wakeup and wake forwarding
- Advanced TSN
- IEEE 1588v2/802.1AS time synchronization
- Hardware time-stamping with integrated phase correction
- Highly accurate 1pps signal (±15ns)
- Audio clocking
- AVB IEEE 1722 media clock generation capability
- Phase synchronized wall clock output: 1KHz to 50MHz
- I2S and TDM8 SCLK/FSYNC/MCLK clock generation
- Open Alliance TC12 Interoperability and EMC compliant
- OA EMC compliant
- SAE J2962-3 EMC Compliant
- Integrated LPF on MDI pins
- MAC interfaces: RGMII and SGMII
- Supported I/O voltages: 3.3V, 2.5V, and 1.8V
- Pin compatible with TI’s 100BASE-T1 PHYs and 1000BASE-T1 PHYs
- Single board design for 100BASE-T1 and 1000BASE-T1 with required BOM change
- Diagnostic toolkit
- Temperature, voltage, ESD monitor
- Data throughput calculator: inbuilt MAC packet generator, counter and error checker
- Signal quality indicator
- TDR based open and short cable fault detection
- Loopback modes
- AEC-Q100 qualified
- IEC61000-4-2 ESD: ±8kV contact discharge
The DP83TG721-Q1 is an IEEE 802.3bp and Open Alliance compliant automotive 1000Base-T1 Ethernet physical layer transceiver. The DP83TG721-Q1 provides all physical layer functions needed to transmit and receive data over unshielded/shielded single twisted-pair cables. The device provides xMII flexibility with support for RGMII and SGMII MAC interfaces.
DP83TG721-Q1 supports OA TC10 low-power sleep feature (with wake forwarding) to reduce system power consumption when communication is not required. This device offers the Diagnostic Tool Kit, with an extensive list of real-time monitoring tools, debug tools and test modes.
DP83TG721-Q1 integrates IEEE 1588v2/802.1AS hardware time stamping and fractional PLL enabling highly accurate time synchronization. The fractional PLL enables frequency/phase synchronization of the Wall Clock eliminating need for external VCXO and generating wide range of time synchronized frequencies needed for Audio, Video and other ADAS applications.
DP83TG721-Q1 also integrates IEEE 1722 CRF decode to generate Media Clock (wall clock synchronized) for AVB and other Audio standards. The DP83TG721-Q1 is also capable of generating FSYNC/SCLK (wall clock synchronized) for I2S/TDM8 interface needed for audio applications.
The DP83TG721-Q1 is compatible to TI’s 100BASE-T1 PHYs and 1000BASE-T1 PHYs enabling design scalability with single board for both speeds.
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技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | DP83TG721x-Q1 1000BASE-T1 Automotive Ethernet PHY With Advanced TSN and AVB 数据表 (Rev. B) | PDF | HTML | 2026-9-25 | ||
| 白皮书 | 基于以太网 PHY 的时间敏感网络 | PDF | HTML | 英语版 | PDF | HTML | 2025-1-24 | |
| 应用简报 | 使用单线对以太网推动人形机器人发展 | PDF | HTML | 英语版 | PDF | HTML | 2025-1-8 | |
| 应用手册 | 如何将 Linux 驱动程序集成到您的系统中 | PDF | HTML | 英语版 | PDF | HTML | 2024-12-4 | |
| 应用手册 | SGMII 疑难解答指南 | PDF | HTML | 英语版 | PDF | HTML | 2024-11-6 | |
| 应用手册 | 基于 Linux® 的基本以太网接口调试 | PDF | HTML | 英语版 | PDF | HTML | 2024-10-14 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
DP83TG721EVM-MC — DP83TG721 1000Base-T1 转 1000Base-T 介质转换器评估模块
DP83TG721-Q1-DESIGN — DP83TG721-Q1 1000BASE-T1 PHY with TC-10 & IEEE 1588v2 / 802.1AS
ETHERNET-SW — 以太网 PHY 驱动程序和工具
德州仪器 (TI) 以太网物理层 (PHY) 收发器的驱动程序支持通过串行管理接口 (MDC/MDIO) 进行通信，从而配置和读取 PHY 寄存器。Linux 和 RTOS 驱动程序可在我们的 GitHub 上找到。
TIDA-020071 — TDA4 四通道汽车级 PHY RGMII 参考设计
该参考设计通过 RGMII 以太网扩展连接器与 Jacinto™ 7 处理器 EVM 板连接。通过 TI 的汽车级以太网物理层 (PHY) 添加四个汽车以太网连接。该设计展示了采用 TI DP83TC818S-Q1 100Mbps 和 DP83TG721S-Q1 1000Mbps 单线对以太网 (SPE) PHY 的实现方案。耦合网络用于将 12V 电压耦合到数据线。
TIDA-020079 — 区域参考设计
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| VQFN (RHA) | 36 | Ultra Librarian |
订购和质量
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