The CDCM7005-SP is a high-performance, low phase noise and low skew clock synchronizer
that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled
oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the
feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to
VC(X)O as VC(X)O_IN / PRI_REF = (N × P) / M or VC(X)O_IN / SEC_REF = (N × P) / M.
VC(X)O_IN clock operates up to 2 GHz. Through the selection of external VC(X)O and loop
filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system
The CDCM7005-SP can lock to one of two reference clock inputs (PRI_REF and SEC_REF),
supports frequency hold-over mode and fast-frequency-locking for fail-safe and increased system
redundancy. The outputs of the CDCM7005-SP are user definable and can be any combination of up to
five LVPECL outputs or up to 10 LVCMOS outputs. The LVCMOS outputs are arranged in pairs (Y0A:Y0B,
Y1A:Y1B, Ω), so that each pair has the same frequency. But each output can be separately inverted
and disabled. The built in synchronization latches ensure that all outputs are synchronized for low
All device settings, like outputs signaling, divider value, input selection, and many
more, are programmable by SPI (3-wire serial peripheral interface). SPI allows individually control
of the device settings.
The device operates in a 3.3-V environment and is characterized for operation from –55°C
to 125°C (Tcase).