产品详情

Function Single-loop PLL Number of outputs 5 Output frequency (min) (MHz) 0 Output frequency (max) (MHz) 1500 Input type LVCMOS (REF_CLK), LVPECL (VCXO_CLK) Output type LVCMOS, LVPECL Supply voltage (min) (V) 3 Supply voltage (max) (V) 3.6 Features Programmable Delay Rating Space Operating temperature range (°C) -55 to 125 Number of input channels 2
Function Single-loop PLL Number of outputs 5 Output frequency (min) (MHz) 0 Output frequency (max) (MHz) 1500 Input type LVCMOS (REF_CLK), LVPECL (VCXO_CLK) Output type LVCMOS, LVPECL Supply voltage (min) (V) 3 Supply voltage (max) (V) 3.6 Features Programmable Delay Rating Space Operating temperature range (°C) -55 to 125 Number of input channels 2
CFP (HFG) 52 363.474225 mm² 19.065 x 19.065
  • High Performance LVPECL and LVCMOS PLL
    Clock Synchronizer
  • Two Reference Clock Inputs (Primary and
    Secondary Clock) for Redundancy Support
    With Manual or Automatic Selection
  • Accepts LVCMOS Input Frequencies Up to
    200 MHz
  • VCXO_IN Clock is Synchronized to One of the
    Two Reference Clocks
  • VCXO_IN Frequencies Up to 2 GHz (LVPECL)
  • Outputs can be a Combination of LVPECL and
    LVCMOS (Up to Five Differential LVPECL
    Outputs or Up to 10 LVCMOS Outputs)
  • Output Frequency is Selectable by x1, /2, /3, /4,
    /6, /8, /16 on Each Output
    Individually
  • Efficient Jitter Cleaning from Low PLL Loop
    Bandwidth
  • Low Phase Noise PLL Core
  • Programmable Phase Offset (PRI_REF and
    SEC_REF to Outputs)
  • Wide Charge Pump Current Range From
    200 µA to 3 mA
  • Analog and Digital PLL Lock Indication
  • Provides VBB Bias Voltage Output for Single-
    Ended Input Signals (VCXO_IN)
  • Frequency Hold Over Mode Improves Fail-Safe
    Operation
  • Power-Up Control Forces LVPECL Outputs to Tri-
    State at VCC < 1.5 V
  • SPI Controllable Device Setting
  • 3.3-V Power Supply
  • High-Performance 52 Pin Ceramic Quad Flat
    Pack (HFG)
  • Rad-Tolerant : 50 kRad (Si) TID
  • QML-V Qualified, SMD 5962-07230
  • Military Temperature Range: –55°C to 125°C Tcase
  • Engineering Evaluation (/EM) Samples are
    Available(1)
  • High Performance LVPECL and LVCMOS PLL
    Clock Synchronizer
  • Two Reference Clock Inputs (Primary and
    Secondary Clock) for Redundancy Support
    With Manual or Automatic Selection
  • Accepts LVCMOS Input Frequencies Up to
    200 MHz
  • VCXO_IN Clock is Synchronized to One of the
    Two Reference Clocks
  • VCXO_IN Frequencies Up to 2 GHz (LVPECL)
  • Outputs can be a Combination of LVPECL and
    LVCMOS (Up to Five Differential LVPECL
    Outputs or Up to 10 LVCMOS Outputs)
  • Output Frequency is Selectable by x1, /2, /3, /4,
    /6, /8, /16 on Each Output
    Individually
  • Efficient Jitter Cleaning from Low PLL Loop
    Bandwidth
  • Low Phase Noise PLL Core
  • Programmable Phase Offset (PRI_REF and
    SEC_REF to Outputs)
  • Wide Charge Pump Current Range From
    200 µA to 3 mA
  • Analog and Digital PLL Lock Indication
  • Provides VBB Bias Voltage Output for Single-
    Ended Input Signals (VCXO_IN)
  • Frequency Hold Over Mode Improves Fail-Safe
    Operation
  • Power-Up Control Forces LVPECL Outputs to Tri-
    State at VCC < 1.5 V
  • SPI Controllable Device Setting
  • 3.3-V Power Supply
  • High-Performance 52 Pin Ceramic Quad Flat
    Pack (HFG)
  • Rad-Tolerant : 50 kRad (Si) TID
  • QML-V Qualified, SMD 5962-07230
  • Military Temperature Range: –55°C to 125°C Tcase
  • Engineering Evaluation (/EM) Samples are
    Available(1)

The CDCM7005-SP is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VC(X)O as VC(X)O_IN / PRI_REF = (N × P) / M or VC(X)O_IN / SEC_REF = (N × P) / M.

VC(X)O_IN clock operates up to 2 GHz. Through the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements.

The CDCM7005-SP can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequency hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The outputs of the CDCM7005-SP are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS outputs. The LVCMOS outputs are arranged in pairs (Y0A:Y0B, Y1A:Y1B, Ω), so that each pair has the same frequency. But each output can be separately inverted and disabled. The built in synchronization latches ensure that all outputs are synchronized for low output skew.

All device settings, like outputs signaling, divider value, input selection, and many more, are programmable by SPI (3-wire serial peripheral interface). SPI allows individually control of the device settings.

The device operates in a 3.3-V environment and is characterized for operation from –55°C to 125°C (Tcase).

The CDCM7005-SP is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VC(X)O as VC(X)O_IN / PRI_REF = (N × P) / M or VC(X)O_IN / SEC_REF = (N × P) / M.

VC(X)O_IN clock operates up to 2 GHz. Through the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements.

The CDCM7005-SP can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequency hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The outputs of the CDCM7005-SP are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS outputs. The LVCMOS outputs are arranged in pairs (Y0A:Y0B, Y1A:Y1B, Ω), so that each pair has the same frequency. But each output can be separately inverted and disabled. The built in synchronization latches ensure that all outputs are synchronized for low output skew.

All device settings, like outputs signaling, divider value, input selection, and many more, are programmable by SPI (3-wire serial peripheral interface). SPI allows individually control of the device settings.

The device operates in a 3.3-V environment and is characterized for operation from –55°C to 125°C (Tcase).

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类型 标题 下载最新的英语版本 日期
* 数据表 CDCM7005-SP 3.3-V High Performance Rad-Tolerant Class V, Clock Synchronizer and Jitter Cleaner 数据表 (Rev. G) PDF | HTML 2015年 12月 3日
* SMD CDCM7005-SP SMD 5962-07230 2016年 7月 8日
* 辐射与可靠性报告 CDCM7005MHFG-V Radiation Test Report 2014年 11月 12日
应用简报 经 DLA 批准的 QML 产品优化 PDF | HTML 英语版 PDF | HTML 2024年 5月 24日
更多文献资料 TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. A) 2023年 8月 31日
应用手册 单粒子效应置信区间计算 (Rev. A) PDF | HTML 英语版 (Rev.A) PDF | HTML 2022年 12月 2日
应用手册 重离子轨道环境单粒子效应估算 (Rev. A) PDF | HTML 英语版 (Rev.A) PDF | HTML 2022年 11月 30日
电子书 电子产品辐射手册 (Rev. B) 2022年 5月 7日
选择指南 TI Space Products (Rev. I) 2022年 3月 3日
电子书 电子产品辐射手册 (Rev. A) 2019年 5月 21日
EVM 用户指南 CDCM7005EVM-CVAL Evaluation Module (EVM) User's Guide 2018年 9月 11日
应用手册 Phase Noise/Phase Jitter Performance of CDCM7005 2005年 7月 26日

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CDCM7005EVM-CVAL — CDCM7005-SP 评估模块

CDCM7005 是一款高性能、低相位噪声、低偏差的时钟同步器,可将板载电压控制晶体振荡器 (VC(X)O) 频率与外部参考时钟保持同步。该器件的运行频率高达 2 GHz。PLL 环路带宽和阻尼因数可进行调节以满足不同的系统需求,方法是选择外部 VC(X)O、环路滤波器组件、PFD 的频率以及电荷泵电流。五个差动 LVPECL 和五个 LVCMOS 对输出中的每一个均可通过串行外设接口 (SPI) 进行编程。该 SPI 可以单独控制频率和启用/禁用每个输出的状态。由于系统需要使用外部组件(例如,环路滤波器和 VC(X)O),因此该 EVM (...)
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SGLC002 CDCM7005-SP EVM GUI

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时钟抖动清除器和同步器
CDCM7005-SP 耐辐射加固保障 (RHA) 3.3V 高性能时钟抖动清除器和同步器
硬件开发
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CDCM7005EVM-CVAL CDCM7005-SP 评估模块
仿真模型

CDCM7005-SP IBIS MODEL A

SLLM295.ZIP (36 KB) - IBIS Model
仿真模型

CDCM7005-SP IBIS MODEL B

SLLM296.ZIP (36 KB) - IBIS Model
仿真模型

CDCM7005-SP IBIS MODEL C

SLLM297.ZIP (36 KB) - IBIS Model
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时钟树架构是一款时钟树综合工具,可根据您的系统要求生成时钟树解决方案,从而帮助您简化设计流程。该工具从庞大的时钟产品数据库中提取数据,然后生成系统级多芯片时钟解决方案。
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