CDCE18005
- Universal Input Buffers That Accept LVPECL, LVDS, or LVCMOS Level Signaling
- Fully Configurable Outputs Including Frequency, Output Format, and Output Skew
- Output Multiplexer That Serves as a Clock Switch Between the Three Reference Inputs
and the Outputs - Clock Generation Via AT-Cut Crystal
- Integrated EEPROM Determines Device Configuration at Power-up
- Low Additive Jitter Performance
- Universal Output Blocks Support up to 5 Differential, 10 Single-ended, or
Combinations of Differential or Single-ended:- Low Additive Jitter
- Output Frequency up to 1.5 GHz
- LVPECL, LVDS, LVCMOS, and Special High Output Swing Modes
- Independent Output Dividers Support Divide Ratios from 1–80
- Independent limited Coarse Skew Control on all Outputs
- Flexible Inputs:
- Two Universal Differential Inputs Accept Frequencies up to 1500 MHz (LVPECL),
800 MHz (LVDS), or 250 MHz (LVCMOS). - One Auxiliary Input Accepts Crystal. Auxiliary Input Accepts Crystals in the Range of
2 MHz–42 MHz - Clock Generator Mode Using Crystal Input.
- Two Universal Differential Inputs Accept Frequencies up to 1500 MHz (LVPECL),
- Typical Power Consumption 1W at 3.3V
- Offered in QFN-48 Package
- ESD Protection Exceeds 2kV HBM
- Industrial Temperature Range –40°C to 85°C
The CDCE18005 is a high performance clock distributor featuring a high degree of configurability via a SPI interface, and programmable start up modes determined by on-chip EEPROM. Specifically tailored for buffering clocks for data converters and high-speed digital signals, the CDCE18005 achieves low additive jitter in the 50 fs RMS(1) range. The clock distribution block includes five individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to a unique output frequency (up to 1.5 GHz(2)
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| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | Five/Ten Output Clock Programmable Buffer 数据表 (Rev. B) | 2012-11-21 | |||
| 用户指南 | Low Phase Noise Clock Evaluation Module — up to 1.5 Ghz | 2008-11-11 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
评估板
CDCE18005EVM — CDCE18005EVM 评估模块
CDCE18005 是高性能时钟发生器和分配器，它具有高度可配置性（通过 SPI 接口进行配置）和由片上 EEPROM 确定的可编程启动模式。专为数据转换器和高速数字信号的缓冲时钟而设计，CDCE18005 实现了 50 fs 范围以内的低附加抖动。时钟分配块包含 5 个独立的可编程输出，它们可以配置成提供不同的输出格式组合（LVPECL、LVDS、LVCMOS）。也可以通过可编程延迟块将每个输出编程为独特的输出频率（高达 1.5GHzGHz）和偏移关系。如果所有输出都采用单端模式（例如 LVCMOS）进行配置，则 CDCE18005 可支持多达 10 路输出。每个输出都可以选择 3 (...)
支持软件
SCAC106 — CDCE18005 EVM Control Software installer
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| VQFN (RGZ) | 48 | Ultra Librarian |
订购和质量
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