Designing With the C2000™ Embedded Pattern Generator (EPG)

Trademarks

C2000 is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

1 Introduction

The Embedded Pattern Generator (EPG) module is a customizable pattern and clock generator that could serve many test and application scenarios that require a simple pattern generator or a periodic clock generator. The EPG module can also be used to capture an incoming serial stream of data. The EPG module allows users to design new clock generators,pulse width modulators (PWMs), serial communication modules, and so forth.

The EPG module can be used as an independent peripheral or it can be used along side other peripherals such as CAN. When used alongside other peripherals, such as CAN, EPG can provide signal patterns for testing and running diagnostic inside the C2000™ device.

1.1 Supplementary Information

For more information on the EPG module on a specific C2000 device, see the device-specific data sheet and the corresponding Technical Reference Manual (TRM).

This application report was written using the TMS320F28003x family of devices. The data sheet and TRM used for this application report are listed below:

Additional support is provided by the TI E2E™ Community.

2 Clock Generator

The EPG can be used to generate clock signals. These clock signals can be used internally by the EPG (the EPG SIGGENx modules), or be exported out of the EPG through EPGOUTx signals. If exported out of the EPG through the EPGOUTx signals, then these clock signals can be used by other peripherals through the XBARs (EPGOUTs are connected to Output XBAR and CLB Output XBAR for F28003x) or be sent out of the device through GPIOs.

For example, for F28003x, EPG1 EPGOUT0 and EPGOUT1 are connected to Output XBAR. Therefore, EPGOUT0 and EPGOUT1 can be sent out of the device through GPIOs configured for Output XBAR. Also, on F28003x, the EPG1 EPGOUT2 and EPGOUT3 are connected to CLB Output XBAR, therefore; they can also be sent out of the device through GPIOs.

The EPG CLKGEN modules generate two version of output signals. The DCLK outputs are approximately 50% duty while the GCLK are the gated clocks. DCLKs can be exported out of the EPG module through EPGOUTx signals. GCLKs are used by the SIGGEN modules inside the EPG.

2.1 Generating Two Offset Clocks

Each CLKGEN module can generate four GCLK and four DCLK outputs. Each of the four output clocks have their own OFFSET. All clocks within the same CLKGEN module share the same clock divider counter (CLKDIVx_CTL0.PRD).

To generate two offset clocks based on EPGCLK, there is no need for an external input to the EPG. That means the EPGIN signals are not used and, therefore, no configuration of the Input XBAR is needed. In the F28003x device, EPG1 EPGIN1 to EPGIN4 are sourced from Input XBAR INPUT13 to INPUT16, but in this example, those resources from Input XBAR can be used for other purposes.

To generate the two offset clock signals, CLKGEN0 of EPG1 is used. CLKGEN0 of EPG1 will generate CLKOUT0_DCLK as the reference clock signal, and CLKOUT1_DCLK as the offset clock signal.

The EPGOUT0 and EPGOUT1 MUXes must configured to output:

EPGOUT0: CLKGEN0 → CLKOUT0_DCLK
EPGOUT1: CLKGEN0 → CLKOUT1_DCLK

This is show in Figure 2-1.

Figure 2-1 Select CLKGEN0 Outputs for EPGOUT

Next, CLKGEN0 must be configured to divide the EPGCLK down using CLDIV0_CTL0.PRD and create offsets by configuring the CLKDIV0_CLKOFFSET.CLK0OFFSET and CLKDIV0_CLKOFFSET.CLK1OFFSET. In this example EPGCLK is divided by 100, and the two CLKOUT0 and CLKOUT1 are offset by 25.

CLDIV0_CTL0.PRD = 100 - 1
CLKDIV0_CLKOFFSET.CLK0OFFSET = 0
CLKDIV0_CLKOFFSET.CLK1OFFSET = 25

To output EPGOUT0 and EPGOUT1 to GPIOs, Output XBAR must be used. Two Output XBAR OUTPUTs must be configured to select the EPGOUT0 and EPGOUT1 signals, and the device PinMux must be configured to use Output XBAR on the corresponding GPIOs.

For F28003x, SYSCLK is set to 120 MHz. With a clock divider of 100, the frequency of the generated CLKOUT0_DCLK and CLKOUT1_DCLK are 1.2 MHz. The clock offset of 25 for CLKOUT1_DCLK, offsets the signal from CLKOUT0_DCLK by 200 ns.

If the SIGGEN0 module is configured for any mode other than BIT-BANG mode, the clock generation will stop until the SIGGEN0 module starts a ROTATE or SHIFT. Therefore, inserting the line below will disable the clock generation in this example.

EPG_setSignalGenMode(EPG1_BASE, EPG_SIGGEN0, EPG_SIGGEN_MODE_SHIFT_RIGHT_ONCE);

Note: Since CLKGEN0 is used, the clock generation is only active when SIGGEN0 is in BIT-BANG mode, or if SIGGEN0 is in any other mode, an active SHIFT or RATATE must be in progress for clocks to get generated. For F28003x, if CLKGEN1 was used, since there is no SIGGEN1 module, the clock generation is ALWAYs active.

C2000Ware example 7 showcases this example configuration.

Figure 2-2 Two Offset Clocks

3 Signal Generator

EPG signal generators (SIGGENx) modules can generate or capture complex digital patterns. SIGGENx modules can be configured to many different modes (rotate right mode, shift right mode, and so forth).

SIGGENx modules are clocked from the CLKGENx modules. Therefore, the CLKGENx modules must be configured.

A simple pattern that can be generated by a SIGGEN module is same pattern as the two offset clocks examples previously generated by the CLKGEN module.