SPRACY7 October   2021 TMS320F2800132 , TMS320F2800133 , TMS320F2800135 , TMS320F2800137 , TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Supplementary Information
  3. 2Clock Generator
    1. 2.1 Generating Two Offset Clocks
  4. 3Signal Generator
    1. 3.1 Two Offset Clocks Generated by the SIGGEN0 Module
    2. 3.2 Generate Serial Data With Rotate Mode
      1. 3.2.1 Rotate Right Once - CPOL = 0, CPHA = 1
      2. 3.2.2 Rotate Right Once - CPOL=0, CPHA=0
      3. 3.2.3 Rotate Right Once - CPOL=1, CPHA=1
      4. 3.2.4 Rotate Right Once - CPOL=1, CPHA=0
      5. 3.2.5 Shift Right Once - CPOL=1, CPHA=0
      6. 3.2.6 Shift Right Once - CPOL=0, CPHA=0
  5. 4Summary
  6. 5References

3.2.1 Rotate Right Once - CPOL = 0, CPHA = 1

The SPI data serial bit stream is placed in SIGGEN0_DATA0[15:0], while the SPI clock serial bit stream is placed in SIGGEN0_DATA0[31:16]. SIGGEN0_DATA1 is not used in this mode.

Note: SIGGEN0_DATA1[31:0] and SIGGEN0_DATA0[31:0] are concatenated inside the SIGGEN module to create DATA[63:0].

The clock and data bit stream for CPOL=0 and CPHA=1 is shown below:

//
// Data
//
#define SIG_GEN_DATA0_0_15    0b1111000011001111U

//
// Clock - Data latched on rising edge, during idle CLK is LOW
//
#define SIG_GEN_DATA0_16_31   0b1010101010101010U

For the serial data bit stream, each TWO consecutive bits are the same. This allows 256 different patterns (8-bit data) to be generated. For the serial clock bit steam, the transition from 0 to 1 occurs during in between the serial data bit repetition.

Figure 3-7 EPG SIGGEN Bit Stream for SPI CLK and DATA (CPOL=0, CPHA=1)

In ROTATE RIGHT ONCE mode, the clock signal generated will begin with the LOW (0) state as soon as the SIGGEN module in enabled. After the 16 rotate operations are completed on the DATA[63:0] of the SIGGEN0 module, the SIGGEN0 module will reload the SIGGEN0_DATA0 and SIGGEN0_DATA1 registers into the active registers. This means that the IDLE state of the clock is LOW (0).

The idle state of the SIGGEN generated serial data is SIGGEN0_DATA0[0] and the idle state of generated serial clock is SIGGEN0_DATA0[16]. This means that the idle state of the clock signal will always be LOW, while the idle state of the data signal will depend on the data.

Figure 3-8 Rotate Right Once - CPOL=0, CPHA=1

After a full BIT-LENGTH shift has been completed, the SIGGEN module is disabled. The user can fill in the new data in SIGGEN0_DATA0 and re-enable the SIGGEN module to generate new data. The EPG interrupt status flags can be checked to determine if the SIGGEN module has completed all operations, or to determine whether new data should be loaded into the SIGGEN module.

epg1_gintsts = EPG_getInterruptStatus(EPG1_BASE);
if (epg1_gintsts & EPG_INT_SIGGEN0_DONE){
    EPG_clearInterruptFlag(EPG1_BASE, epg1_gintsts);
    EPG_setData0Word(EPG1_BASE, EPG_SIGGEN0, (SIG_GEN_DATA0_0_15 | (uint32_t)SIG_GEN_DATA0_16_31 << 16));
    EPG_enableSignalGen(EPG1_BASE, EPG_SIGGEN0);
}

Interrupts can also be generated by the EPG module. For the F28003x, the EPG interrupt is the SYS_ERROR interrupt (INT_SYS_ERR).