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  • TMUX741xEVM and TMUX746EVM User's Guide

    • SCDU019 June   2021

       

  • CONTENTS
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  • TMUX741xEVM and TMUX746EVM User's Guide
  1.   Abstract
  2.   Trademarks
  3. 11. Introduction
    1. 1.1 Information About Cautions and Warnings
  4. 23. Features of This EVM
  5. 34. TMUX741-746EVM Setup
  6. 45. TMUX741-746EVM Jumper Connections and Test Points
  7. 56. Schematics
  8. 67. Bill of Materials
  9. 78. PCB Layouts
  10. 8Related Documentation
  11. IMPORTANT NOTICE
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EVM USER'S GUIDE

TMUX741xEVM and TMUX746EVM User's Guide

Abstract

This document is the EVM user’s guide for the TMUX741-746EVM which provides a board for quick DC parmeter testing for the TMUX741x and TMUX746x families in the QFN and TSSOP package families.

Trademarks

All trademarks are the property of their respective owners.

1 1. Introduction

This user’s guide describes the TMUX741-746 evaluation module (EVM) and its intended use. This board allows for the quick prototyping and DC characterization of TI’s TMUX741x/TMUX746x Line of parts in either QFN (RRP) or TSSOP (PW) packages. Figure 1-1 and Figure 1-2 show the top and bottom sides of the board respectively.

GUID-20210615-CA0I-HPQB-MT5F-Z4PKV6SVDBG8-low.jpg Figure 1-1 TMUX741-746EVM Top Side View
GUID-20210615-CA0I-DJTT-KPXS-NFGBH3V8DKDG-low.jpg Figure 1-2 TMUX741-746EVM Bottom Side View

1.1 Information About Cautions and Warnings

The information in the warning statement is provided for personal protection and the information in the caution statement is provided to protect the equipment from damage. Read each caution and warning statement carefully.

GUID-ED3721F4-D5D2-43AA-98F7-19FF9FDCAB2C-low.gif

This EVM contains components that can ptentially be damaged by electrostatic discharge. Always transport and store the EVM in its supplied ESD bad when not in suse. Handle using an antistatic wristband. Operate on an antistatic work surface. For more information on proper handling, see Electrostatic Discharge (ESD).

2 3. Features of This EVM

The EVM has the following features:

  • Four power supply decoupling capacitors from VDD to Ground (2 × 3.3 µF, 1 µF, 0.1 µF)
  • One additional power supply decoupling capacitor pad from VDD to Ground (0.1 µF)
  • One power supply decoupling capacitors from VSS to Ground (2 × 3.3 µF, 1 µF, 0.1 µF)
  • One additional power supply decoupling capacitor pad from VDD to Ground (0.1 µF)
  • Protection diode pads available near VDD and VSS input.
  • 10 µF supply decoupling capacitor to Ground on both VFP and VFN supplies
  • Protection diode pads available near VFP and VFN inputs
  • Up to four auxiliary pathways available with jumpers
  • Up to eight analog I/O pathways available
  • All analog I/O pathways have pads available to load device
  • All analog I/O pathways have pads available to support SMA connections to device.
  • Fault indicator flag LED circuit included on EVM

3 4. TMUX741-746EVM Setup

  1. If the default conditions on the board is not what you desired please refer to the following table to set up the Auxiliary pathways which can be either VFP, VFN, SEL, DR, or NC depending on device installed.
    Jumper on Pathway Possible Signal Pull Up Resistor Pad ID Load Resistor Pad ID Load Capacitor Pad ID Additional Capacitor Pad ID
    J7 VFN / SEL R4 R17 C17 C10
    J5 VFN / SEL N/A N/A N/A N/A
    J8 VFP / SEL R6 R18 C18 C9
    J6 VFP / SEL N/A N/A N/A N/A
    J9 DR / SEL R7 R19 C19 N/A
    J10 NC / SEL R8 R20 C20 N/A
  2. If VFP and VFN are used in the application, attach a shunt on J5 and J6 to the appropriate VFP/VFN source.
  3. Next, use the following table to set up the desired configuration of the analog channels:
    Jumper on Pathway Pull Down Resistor Pad ID Pull Up Resistor Pad ID Load Resistor Pad ID Load Capacitor Pad ID TVS Diode Pad ID
    J11 R33 R21 R34 C21 D6
    J12 R35 R22 R36 C22 D7
    J13 R37 R23 R38 C23 D8
    J14 R39 R24 R40 C24 D9
    J15 R53 R41 R54 C25 D10
    J16 R55 R42 R56 C26 D11
    J17 R57 R43 R58 C27 D12
    J18 R59 R44 R60 C28 D13
  4. Next, solder down the chosen TMUX74xx in either a PW or QFN package that is to be tested.
  5. If using dual supplies, connect shunt from VSS to PAD on J19.
  6. If using single supplies, connect shunt from VSS to GND on J4.
  7. Next, power the board through J2. Follow the specific device data sheet as to what range the voltage should be set to.
  8. If VFP/VFN pins are used in the application and are using an external source power this through J3.
  9. If the fault flag voltage (VFF) is used in the application, connect and power up this source through J1.

4 5. TMUX741-746EVM Jumper Connections and Test Points

  1. The auxiliary lines on the EVM have 3 prong jumpers attached to them. These are labeled on the board but are also listed in the following table:
    Jumper ID Jumper Pin 1 Jumper Pin 2 Jumper Pin 3 Test Point 1 Test Point 2
    J7 VDD VFN/SEL GND TP17 TP18
    J8 VDD VFP/SEL GND TP19 TP20
    J9 VDD DR/SEL GND TP21 TP22
    J10 VDD NC/SEL GND TP23 TP24
  2. The analog lines on the have 6 prong jumpers attached to them in a 2 × 3 formation. Only 4 pins have signals attached to them. For reference this document refers to jumper pins that are closest to the IC as Interior Jumper Pins and pins that face away from the IC as Exterior Jumper Pins. All interior pins are used, only the middle exterior pin is used. Please see the following table for connections.
    Jumper ID Top Interior Pin Mid. Interior Pin Bottom Interior Pin Mid. Exterior Pin Test Point 1 Test Point 2
    J11 VDD D1 VSS GND TP25 TP26
    J12 VDD S1 VSS GND TP27 TP28
    J13 VDD S4 VSS GND TP29 TP30
    J14 VDD D4 VSS GND TP31 TP32
    J15 VDD D2 VSS GND TP33 TP34
    J16 VDD S2 VSS GND TP35 TP36
    J17 VDD S3 VSS GND TP37 TP38
    J18 VDD D3 VSS GND TP39 TP40
  3. Finally, the remaining test points and their location on board.
    Test Point ID Signal Net Attached to Test Point
    TP4 VFN_V
    TP3 VFP_V
    TP11 GND
    TP10 GND
    TP7 VSS
    TP6 VDD
    TP5 VFF
    TP12 GND
    TP13 GND
    TP14 GND
    TP2 VSS
    TP1 VDD
    TP15 GND
    TP16 GND

5 6. Schematics

Figure 5-1 shows the schematic without DNP/DNI markings. Figure 5-2 shows the scheamtic with DNP/DNI markings. Figure 5-3 shows mechanical hardware and overlays.

GUID-20210615-CA0I-S6WV-2ZBM-LS9LGQHT1SBZ-low.png Figure 5-1 TMUX741-746EVM Schematic without DNP/DNI Markings
GUID-20210615-CA0I-NBXR-XSDK-3NMLZ8CLZLQ9-low.png Figure 5-2 TMUX741-746EVM with DNP/DNI Markings
GUID-20210615-CA0I-0JRM-K7W4-MNLBHBV9RR1M-low.png Figure 5-3 TMUX741-746EVM Mechanical Hardware and Overlays

 

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