ZHCSXY6B May   2005  – March 2025 TPIC6596

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Dissipation Rating Table
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Electrical Characteristics
    5. 5.5 Switching Characteristics
    6. 5.6 Thermal Resistance Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial-In Interface
      2. 7.3.2 Clear Register
      3. 7.3.3 Output Control
      4. 7.3.4 Cascaded Application
      5. 7.3.5 Current Limit Function
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating with Vcc < 4.5V
      2. 7.4.2 Operating with 5.5V < Vcc ≤ 7V
  9. 8 Device and Documentation Support
    1. 8.1 接收文档更新通知
    2. 8.2 支持资源
    3. 8.3 Trademarks
    4. 8.4 静电放电警告
    5. 8.5 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.5 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETERTEST CONDITIONSMINTYPMAXUNIT
tPLHPropagation delay time, low-to-high-level output from G CLL = 30pF = 30pF, IDD = 250mA, See Figure 6-1, Figure 6-2, and Figure 5-7650ns
tPHLPropagation delay time, high-to-low-level output from G200ns
tr Rise time, drain output 230 ns
tf Fall time, drain output 170 ns
tPD Propagation delay time, SRCK↓ to SER OUT CL= 30pF, ID= 250mA, See (3) 50 ns
fSRCK Serial clock frequency CL= 30pF, ID= 250mA, See Figure 6-2 5 MHz
ta Reverse-recovery-current rise time IFF = 250mA, di/dt = 20A/µs. See (1), (2), and Figure 6-3 100 ns
trr Reverse-recovery time 300
(1) Technique must limit TJ − TC to 10°C maximum.
(2) These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
(3) This is the maximum serial clock frequency assuming cascaded operation where serial data is passed from one stage to a second stage. The clock period allows SRCK → SER OUT propagation delay and setup time plus some timing margin