ZHCSO42B December 2015 – July 2021 LM53625-Q1 , LM53635-Q1
PRODUCTION DATA
LM53625-Q1/LM53635-Q1 同步降压稳压器针对汽车应用进行了优化,能够提供 5V、3.3V 的输出电压或可调输出电压。LM53625-Q1/LM53635-Q1 可利用高级高速电路,在 2.1MHz 的固定频率下通过 18V 输入产生 3.3V 的稳压输出。LM53625-Q1/LM53635-Q1 采用创新型架构,在输入电压仅为 3.55V 时也可提供 3.3V 稳压输出。该器件针对汽车和性能驱动型行业客户进行了全方位优化。器件的输入电压高达 36V,容许的瞬态电压高达 42V,因此简化了输入浪涌保护设计。该器件采用通过汽车认证的 Hotrod QFN 可湿性侧面封装,可降低寄生电感和电阻,同时可提高效率、更大限度减小开关节点振铃,并大幅降低电磁干扰 (EMI)。开漏复位输出具有内置的滤波和延迟功能,可提供正确的系统状态指示。凭借这一特性,器件无需使用附加监控元件,这节省了成本和电路板空间。器件可在 PWM 和 PFM 两种模式之间无缝切换,并且低静态电流(3.3V 选项仅为 15µA)确保了其在所有负载条件下均可展现高效率和出色的瞬态响应。
器件名称 | 封装(1) | 封装尺寸 |
---|---|---|
LM53625-Q1 | VQFN-HR (22) | 5.00mm × 4.00mm |
LM53635-Q1 |
Changes from Revision A (May 2016) to Revision B (July 2021)
Changes from Revision * (December 2015) to Revision A (May 2016)
PART NUMBER | OUTPUT VOLTAGE | SPREAD SPECTRUM | PACKAGE QTY | WETTABLE FLANKS |
---|---|---|---|---|
LM53625AQRNLRQ1 | Adjustable | No | 3000 | Y |
LM53625AQRNLTQ1 | Adjustable | No | 250 | Y |
LM536253QRNLRQ1 | 3.3 V | No | 3000 | Y |
LM536253QRNLTQ1 | 3.3 V | No | 250 | Y |
LM536255QRNLRQ1 | 5 V | No | 3000 | Y |
LM536255QRNLTQ1 | 5 V | No | 250 | Y |
LM53625MQRNLRQ1 | Adjustable | Yes | 3000 | Y |
LM53625MQRNLTQ1 | Adjustable | Yes | 250 | Y |
LM53625NQRNLRQ1 | 3.3 V | Yes | 3000 | Y |
LM53625NQRNLTQ1 | 3.3 V | Yes | 250 | Y |
LM53625LQRNLRQ1 | 5 V | Yes | 3000 | Y |
LM53625LQRNLTQ1 | 5 V | Yes | 250 | Y |
LM53625NQURNLRQ1 | 3.3 V | Yes | 3000 | N |
LM53625MQURNLRQ1 | Adjustable | Yes | 3000 | N |
LM53625LQURNLRQ1 | 5 V | Yes | 3000 | N |
PART NUMBER | OUTPUT VOLTAGE | SPREAD SPECTRUM | PACKAGE QTY | Wettable Flanks |
---|---|---|---|---|
LM53635AQRNLRQ1 | Adjustable | No | 3000 | Y |
LM53635AQRNLTQ1 | Adjustable | No | 250 | Y |
LM536353QRNLRQ1 | 3.3 V | No | 3000 | Y |
LM536353QRNLTQ1 | 3.3 V | No | 250 | Y |
LM536355QRNLRQ1 | 5 V | No | 3000 | Y |
LM536355QRNLTQ1 | 5 V | No | 250 | Y |
LM53635MQRNLRQ1 | Adjustable | Yes | 3000 | Y |
LM53635MQRNLTQ1 | Adjustable | Yes | 250 | Y |
LM53635NQRNLRQ1 | 3.3 V | Yes | 3000 | Y |
LM53635NQRNLTQ1 | 3.3 V | Yes | 250 | Y |
LM53635LQRNLRQ1 | 5 V | Yes | 3000 | Y |
LM53635LQRNLTQ1 | 5 V | Yes | 250 | Y |
LM53635MQURNLRQ1 | Adjustable | Yes | 3000 | N |
LM53635NQURNLRQ1 | 3.3 V | Yes | 3000 | N |
PIN | I/O(1) | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | VCC | A | Internal 3.1-V LDO output. Used as supply to internal control circuits. Connect a high-quality 4.7-µF capacitor from this pin to AGND. |
2 | CBOOT | P | Bootstrap capacitor connection for gate drivers. Connect a high quality 470-nF capacitor from this pin to the SW pin. |
3 | SYNC | I | Synchronization input to regulator. Used to synchronize the device switching frequency to a system clock. Triggers on rising edge of external clock; frequency must be in the range of 1.9 MHz and 2.3 MHz. |
4 | PVIN1 | P | Input supply to regulator. Connect input bypass capacitors directly to this pin and PGND pins. Connect PVIN1 and PVIN2 pins directly together at PCB. |
5, 6, 7, 8 | PGND1 | G | Power ground to internal low side MOSFET. These pins must be tied together on the PCB. Connect PGND1 and PGND2 directly together at PCB. Connect to AGND and system ground. |
9 | SW | P | Regulator switch node. Connect to power inductor. |
10, 11, 12, 13 | PGND2 | G | Power ground to internal low side MOSFET. These pins must be tied together. Connect PGND1 and PGND2 directly together at PCB. Connect to AGND and system ground. |
14 | PVIN2 | P | Input supply to regulator. Connect input bypass capacitors directly to this pin and PGND pins. Connect PVIN1 and PVIN2 pins directly together at PCB. |
15 | AVIN | A | Analog VIN, Connect to PVIN1 and PVIN2 on PCB. |
16 | FPWM | I | Do not float. Mode control input of regulator. High = FPWM, low = Automatic light load mode. |
17 | NC | — | No internal connection |
18 | EN | I | Enable input to regulator. High = on, Low = off. Can be connected to VIN. Do not float. |
19 | RESET | O | Open drain reset output flag. Connect to suitable voltage supply through a current limiting resistor. High = regulator OK, Low = regulator fault. Goes low when EN = low. |
20 | AGND | G | Analog ground for regulator and system. All electrical parameters are measured with respect to this pin. Connect to PGND on PCB |
21 | FB | A | Feedback input to regulator. Connect to output voltage node for fixed VOUT options. Connect to feedback voltage divider for adjustable option. |
22 | BIAS | P | Input to auxiliary bias regulator. Connect to output voltage node. |
PARAMETER | MIN | MAX | UNIT |
---|---|---|---|
VIN (AVIN,PVIN1 and PVIN2) to AGND, PGND1 and PGND2(2) | –0.3 | 40 | V |
SW to AGND, PGND(3) | –0.3 | VIN + 0.3 | V |
CBOOT to SW | –0.3 | 3.6 | V |
EN to AGND, PGND(2)(4) | –0.3 | 40 | V |
BIAS to AGND, PGND | –0.3 | 16 | V |
FB to AGND, PGND | –0.3 | 16 | V |
RESET to AGND, PGND | –0.3 | 8 | V |
RESET sink current(5) | 10 | mA | |
SYNC to AGND,PGND(2)(4) | –0.3 | 40 | V |
FPWM to AGND,PGND(4) | –0.3 | 40 | V |
VCC to AGND,PGND | –0.3 | 3.6 | V |
Junction temperature | –40 | 150 | °C |
Storage temperature, Tstg | –40 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q100-002(1) | ±2500 | V |
Charged-device model (CDM), per AEC Q100-011 | ±1000 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Input voltage after start-up(1) | 3.9 | 36 | V | ||
Output voltage for 3.3-V LM53625/35-Q1(2) | 3.4 | V | |||
Output voltage for 5-V LM53625/35-Q1(2) | 5.2 | V | |||
Output adjustment for adjustable version of LM53625/35-Q1(2) | 3.3 | 10 | V | ||
Load current for LM53625-Q1, fixed output option and adjustable | 2.5 | A | |||
Load current for LM53635-Q1, fixed output option and adjustable | 3.5 | A | |||
Junction temperature for 1000-hour lifetime | –40 | 125 | °C | ||
Junction temperature for 408-hour lifetime | –40 | 150 | °C |
THERMAL METRIC(1) | LM53625/35-Q1 | UNIT | |
---|---|---|---|
RNL (VQFN) | |||
22 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 29.4 | °C/W |
RθJC | Junction-to-case (top) thermal resistance | 14.2 | °C/W |
RθJB | Junction-to-board thermal resistance | 5.4 | °C/W |
ψJT | Junction-to-top characterization parameter | 1.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 5.4 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 2.4 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VFB | Initial output voltage accuracy | VIN = 3.8 V to 36 V, TJ = 25°C | –1% | 1% | ||
VIN = 3.8 V to 36 V | –1.5% | 1.5% | ||||
IQ | Operating quiescent current; measured at VIN pin when enabled and not switching(1) | VIN = 13.5 V, VBIAS = 5 V | 6 | µA | ||
VIN = 13.5 V, VBIAS = 5 V, TJ = 85°C | 16 | |||||
IB | Bias current into BIAS pin, enabled, not switching | VIN = 13.5 V, VBIAS = 5 V, FPWM = 0 V | 35 | µA | ||
VIN = 13.5 V, VBIAS = 3.3 V, FPWM = 0 V | 35 | |||||
ISD | Shutdown quiescent current; measured at VIN pin | EN ≤ 0.4 V, TJ = 25°C | 2 | µA | ||
EN ≤ 0.4 V, TJ = 85°C | 3 | |||||
EN ≤ 0.4V, TJ = 150°C | 5 | |||||
VIN-OPERATE | Minimum input voltage to operate | Rising | 3.2 | 3.55 | 3.95 | V |
Falling | 2.95 | 3.25 | 3.55 | |||
Hysteresis | 0.28 | 0.3 | 0.4 | |||
VRESET | RESET upper threshold voltage | Rising, % of VOUT | 105% | 107% | 110% | |
RESET lower threshold voltage | Falling, % VOUT | 92% | 94% | 96.5% | ||
Magnitude of RESET lower threshold from steady state output voltage | Steady-state output voltage and RESET threshold read at the same TJ and VIN | 96% | ||||
VRESET_HYST | RESET hysteresis as a percent of output voltage setpoint | ±1 | ||||
VRESET_VALID | Minimum input voltage for proper RESET function | 50-µA pullup to RESET pin, EN = 0 V, TJ= 25°C | 1.5 | V | ||
VOL | Low level RESET function output voltage | 50-µA pullup to RESET pin, VIN =1.5 V, EN = 0 V | 0.4 | V | ||
0.5-mA pullup to RESET pin, VIN =13.5 V, EN=0 V | 0.4 | |||||
1-mA pullup to RESET pin, VIN =13.5 V, EN=3.3 V | 0.4 | |||||
FSW | Switching frequency | VIN = 13.5 V, center frequency with spread spectrum, PWM operation | 1.85 | 2.1 | 2.35 | MHz |
VIN = 13.5 V, without spread spectrum, PWM operation | 1.85 | 2.1 | 2.35 | |||
FSYNC | Sync frequency range | 1.9 | 2.1 | 2.3 | MHz | |
DSYNC | Sync input duty cycle range | High state input < 5.5 V and > 2.3 V | 25% | 75% | ||
VFPWM | FPWM input threshold voltage | FPWM input high (MODE = FPWM) | 1.5 | V | ||
FPWM input low (MODE = AUTO with diode emulation) | 0.4 | |||||
FPWM input hysteresis | 0.15 | 1 | ||||
FSSS | Frequency span of spread spectrum operation | ±3% | ||||
FPSS | Spread-spectrum pattern frequency(2) | 9 | Hz | |||
FSW-SS | Switching Frequency while in spread spectrum | VIN = 13.5 V, PWM operation | 1.81 | MHz | ||
IFPWM | FPWM leakage current | VIN = 13.5 V, VFPWM = 3.3 V | 1 | µA | ||
VIN = VFPWM = 13.5 V | 5 | |||||
ISYNC | SYNC leakage current | VIN = 13.5 V, VSYNC = 3.3 V | 1 | µA | ||
VIN = VSYNC = 13.5 V | 5 | |||||
IL-HS | High-side switch current limit | LM53625 | 3.5 | 5 | 6.5 | A |
LM53635 | 4.5 | 6 | 7.5 | |||
IL-LS | Low-side switch current limit | LM53625 | 2.5 | 3.5 | 4.1 | A |
LM53635 | 3.5 | 4.5 | 5.1 | |||
IL-ZC | Zero-cross current limit FPWM = low | –0.02 | A | |||
IL-NEG | Negative current limit FPWM = high | –1.5 | ||||
RDSON | Power switch on-resistance | High-side MOSFET RDSON, VIN = 13 V, IL=1A | 60 | 130 | mΩ | |
Low-side MOSFET RDSON, VIN = 13 V, IL=1A | 40 | 80 | ||||
VEN | Enable input threshold voltage - rising | Enable rising | 1.7 | 2 | V | |
VEN_HYST | Enable threshold hysteresis | 0.45 | 0.55 | V | ||
VEN_WAKE | Enable wake-up threshold | 0.4 | V | |||
IEN | EN pin input current | VIN = VEN = 13.5 V | 2 | 5 | µA | |
VCC | Internal VCC voltage | VIN 13.5 V, VBIAS = 0 V | 3.05 | V | ||
VIN = 13.5 V, VBIAS = 3.3 V | 3.15 | |||||
VCC_UVLO | Internal VCC input undervoltage lockout | VIN rising | 2.7 | V | ||
Hysteresis below VCC-UVLO | 185 | mV | ||||
IFB | Input current from FB to AGND | Adjustable LM53625/35-Q1, FB=1 V | 20 | nA | ||
VREF | Reference voltage for adjustable option only | TJ = 25°C | 0.993 | 1 | 1.007 | V |
TJ = –40°C to 125°C | 0.99 | 1 | 1.01 | |||
TJ = –40°C to 150°C | 0.985 | 1 | 1.015 | |||
RRESET | RDSON of RESEToutput | Pull FB pin low. Sink 1-mA at RESET pin | 50 | 85 | Ω | |
VSYNC | VIH | 1.5 | V | |||
VIL | 0.4 | |||||
VHYST | 0.15 | 1 | ||||
TSD | Thermal shutdown thresholds(2) | Rising | 155 | 175 | °C | |
Hysteresis | 15 | |||||
DMAX | Maximum switch duty cycle | Fsw = 2.1 MHz | 80% | |||
While in dropout(2) | 98% |