ZHCSLD2E may   2020  – july 2023 UCC28782

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 描述
  5. Revision History
  6. Device Comparison Table
  7. Pin Configuration and Functions
    1.     Pin Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Detailed Pin Description
      1. 8.3.1  BUR Pin (Programmable Burst Mode)
      2. 8.3.2  FB Pin (Feedback Pin)
      3. 8.3.3  REF Pin (Internal 5-V Bias)
      4. 8.3.4  VDD Pin (Device Bias Supply)
      5. 8.3.5  P13 and SWS Pins
      6. 8.3.6  S13 Pin
      7. 8.3.7  IPC Pin (Intelligent Power Control Pin)
      8. 8.3.8  RUN Pin (Driver and Bias Source for Isolator)
      9. 8.3.9  PWMH and AGND Pins
      10. 8.3.10 PWML and PGND Pins
      11. 8.3.11 SET Pin
      12. 8.3.12 RTZ Pin (Sets Delay for Transition Time to Zero)
      13. 8.3.13 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
      14. 8.3.14 BIN, BSW, and BGND Pins
      15. 8.3.15 XCD Pin
      16. 8.3.16 CS, VS, and FLT Pins
    4. 8.4 Device Functional Modes
      1. 8.4.1  Adaptive ZVS Control with Auto-Tuning
      2. 8.4.2  Dead-Time Optimization
      3. 8.4.3  EMI Dither and Dither Fading Function
      4. 8.4.4  Control Law across Entire Load Range
      5. 8.4.5  Adaptive Amplitude Modulation (AAM)
      6. 8.4.6  Adaptive Burst Mode (ABM)
      7. 8.4.7  Low Power Mode (LPM)
      8. 8.4.8  First Standby Power Mode (SBP1)
      9. 8.4.9  Second Standby Power Mode (SBP2)
      10. 8.4.10 Startup Sequence
      11. 8.4.11 Survival Mode of VDD (INT_STOP)
      12. 8.4.12 Capacitor Voltage Balancing Function
      13. 8.4.13 Device Functional Modes for Bias Regulator Control
        1. 8.4.13.1 Mitigation of Switching Interaction with ACF Converter
        2. 8.4.13.2 Protection Functions for the Bias Regulator
        3. 8.4.13.3 BIN-Pin Related Protections
        4. 8.4.13.4 BSW-Pin Related Protections
      14. 8.4.14 System Fault Protections
        1. 8.4.14.1  Brown-In and Brown-Out
        2. 8.4.14.2  Output Over-Voltage Protection (OVP)
        3. 8.4.14.3  Input Over Voltage Protection (IOVP)
        4. 8.4.14.4  Over-Temperature Protection (OTP) on FLT Pin
        5. 8.4.14.5  Over-Temperature Protection (OTP) on CS Pin
        6. 8.4.14.6  Programmable Over-Power Protection (OPP)
        7. 8.4.14.7  Peak Power Limit (PPL)
        8. 8.4.14.8  Output Short-Circuit Protection (SCP)
        9. 8.4.14.9  Over-Current Protection (OCP)
        10. 8.4.14.10 External Shutdown
        11. 8.4.14.11 Internal Thermal Shutdown
      15. 8.4.15 Pin Open/Short Protections
        1. 8.4.15.1 Protections on CS pin Fault
        2. 8.4.15.2 Protections on P13 pin Fault
        3. 8.4.15.3 Protections on RDM and RTZ pin Faults
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application Circuit
      1. 9.2.1 Design Requirements for a 65-W USB-PD Adapter Application
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage
        2. 9.2.2.2 Transformer Calculations
          1. 9.2.2.2.1 Primary-to-Secondary Turns Ratio (NPS)
          2. 9.2.2.2.2 Primary Magnetizing Inductance (LM)
          3. 9.2.2.2.3 Primary Winding Turns (NP)
          4. 9.2.2.2.4 Secondary Winding Turns (NS)
          5. 9.2.2.2.5 Auxiliary Winding Turns (NA)
          6. 9.2.2.2.6 Winding and Magnetic Core Materials
        3. 9.2.2.3 Clamp Capacitor Calculation
          1. 9.2.2.3.1 Primary-Resonance ACF
          2. 9.2.2.3.2 Secondary-Resonance ACF
        4. 9.2.2.4 Bleed-Resistor Calculation
        5. 9.2.2.5 Output Filter Calculation
        6. 9.2.2.6 Calculation of ZVS Sensing Network
        7. 9.2.2.7 Calculation of BUR Pin Resistances
        8. 9.2.2.8 Calculation of Compensation Network
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1  General Considerations
      2. 11.1.2  RDM and RTZ Pins
      3. 11.1.3  SWS Pin
      4. 11.1.4  VS Pin
      5. 11.1.5  BUR Pin
      6. 11.1.6  FB Pin
      7. 11.1.7  CS Pin
      8. 11.1.8  BIN Pin
      9. 11.1.9  BSW Pin
      10. 11.1.10 AGND Pin
      11. 11.1.11 BGND Pin
      12. 11.1.12 PGND Pin
      13. 11.1.13 EP Thermal Pad
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  14. 13Mechanical, Packaging, and Orderable Information

Capacitor Voltage Balancing Function

ACF contains two energy storage devices on primary and secondary sides. One is the clamping capacitor (CCLAMP) and the other is the output capacitor. When the PWMH signal is enabled, the clamping capacitor voltage (VCLAMP) is close to the reflected output voltage (NPS x VO). When the PWMH is disabled in LPM mode, VCLAMP becomes higher, because some of the leakage energy will be stored on CCLAMP , instead of recycling to the output, as it does in AAM and ABM. During the control mode transition from LPM to ABM, the capacitor voltage balancing current in the first PWMH on time is normally bigger than the following PWMH pulses. If the PWMH on time is too short to discharge CCLAMP, a high di/dt change of the switching current will flow through the transformer winding at the turn-off instant of the high side switch, so the leakage inductance will introduce a high voltage stress across the secondary-side rectifier. Instead of using a strong RC snubber to damp the voltage spike or a lossy bleed resistor in parallel with CCLAMP, UCC28782 automatically extends the first PWMH pulse width around 140% longer than the following PWMH pulse. When the high side switch turns off at lower di/dt current instance, the voltage stress can be reduced, and the efficiency compromise can be eliminated with this new voltage balancing function. Moreover, another possibility of triggering the on-time extension function is under the output voltage ramp down condition, which is a very common transient event of a USB-PD adapter. If the USB-PD controller on the secondary side is able to program the step size of the reference output voltage change, the LPM-to-ABM transition will occur during the voltage change. This behavior allows the VCLAMP to follow the reflected output voltage change, and minimize the voltage stress on the rectifier.

However, some USB-PD controllers can not smoothly change the reference output voltage, but only offer a one-step voltage change to a lower reference level. This rapid change prevents the controller from switching in general, so the chance of voltage balancing during voltage transition is gone. Once the output voltage is settled to the lower level and PWMH is enabled back again, a big voltage difference between VCLAMP and the reflected voltage occurs, and the magnitude of the balancing current may be large enough to create a high voltage stress and damage the secondary rectifier. In order to resolve this issue, UCC28782 utilizes a patent pending unique switching pattern in the survival mode to achieve the capacitor voltage balancing, as shown in the following figure.

With a rapid reference voltage (VREF(Vo)) change, the feedback current (iFB) increases and the controller enters into SBP1 mode. Since this event is like an output overshoot condition, the output voltage feedback loop prevents the ACF from switching and VVDD drops. When VVDD reaches the 13-V survival mode threshold, the unique burst packet contains a series of PWML pulses followed by a long PWMH pulse. The PWML pulse train helps to charge up the bootstrap capacitor voltage, so that the high-side switch can respond to the PWMH command. When the PWMH is in on state, the unbalanced voltage between VCLAMP and the reflected VBIN forces the additional energy to charge up CBIN. The charge current becomes a useful energy source to keep VVDD away from VVDD(OFF). At the same time, CCLAMP can be discharged gradually. Through the multiple survival mode events, VCLAMP can be discharged to be very close to the reflected output voltage, so the voltage stress can be reduced. The minimum number of PWML pulses of the first survival-mode event is 9. The rest survival-mode burst packets contain at least 3 PWML pulses.

GUID-335FB463-A657-444A-89A9-6146F4F62D2A-low.gifFigure 8-33 Capacitor Balancing During Output Voltage Transition