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  • ADC12DJ5200RF 10.4GSPS 单通道或 5.2GSPS 双通道 12 位射频采样模数转换器 (ADC)

    • ZHCSHT7G April   2019  – April 2025 ADC12DJ5200RF

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  • ADC12DJ5200RF 10.4GSPS 单通道或 5.2GSPS 双通道 12 位射频采样模数转换器 (ADC)
  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: DC Specifications
    6. 5.6  Electrical Characteristics: Power Consumption
    7. 5.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 5.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 5.9  Timing Requirements
    10. 5.10 Switching Characteristics
    11. 5.11 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Device Comparison
      2. 6.3.2  Analog Inputs
        1. 6.3.2.1 Analog Input Protection
        2. 6.3.2.2 Full-Scale Voltage (VFS) Adjustment
        3. 6.3.2.3 Analog Input Offset Adjust
      3. 6.3.3  ADC Core
        1. 6.3.3.1 ADC Theory of Operation
        2. 6.3.3.2 ADC Core Calibration
        3. 6.3.3.3 Analog Reference Voltage
        4. 6.3.3.4 ADC Overrange Detection
        5. 6.3.3.5 Code Error Rate (CER)
      4. 6.3.4  Temperature Monitoring Diode
      5. 6.3.5  Timestamp
      6. 6.3.6  Clocking
        1. 6.3.6.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 6.3.6.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 6.3.6.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 6.3.6.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 6.3.6.3.2 Automatic SYSREF Calibration
      7. 6.3.7  Programmable FIR Filter (PFIR)
        1. 6.3.7.1 Dual Channel Equalization
        2. 6.3.7.2 Single Channel Equalization
        3. 6.3.7.3 Time Varying Filter
      8. 6.3.8  Digital Down Converters (DDC)
        1. 6.3.8.1 Rounding and Saturation
        2. 6.3.8.2 Numerically-Controlled Oscillator and Complex Mixer
          1. 6.3.8.2.1 NCO Fast Frequency Hopping (FFH)
          2. 6.3.8.2.2 NCO Selection
          3. 6.3.8.2.3 Basic NCO Frequency Setting Mode
          4. 6.3.8.2.4 Rational NCO Frequency Setting Mode
          5. 6.3.8.2.5 NCO Phase Offset Setting
          6. 6.3.8.2.6 NCO Phase Synchronization
        3. 6.3.8.3 Decimation Filters
        4. 6.3.8.4 Output Data Format
        5. 6.3.8.5 Decimation Settings
          1. 6.3.8.5.1 Decimation Factor
          2. 6.3.8.5.2 DDC Gain Boost
      9. 6.3.9  JESD204C Interface
        1. 6.3.9.1 Transport Layer
        2. 6.3.9.2 Scrambler
        3. 6.3.9.3 Link Layer
        4. 6.3.9.4 8B/10B Link Layer
          1. 6.3.9.4.1 Data Encoding (8B/10B)
          2. 6.3.9.4.2 Multiframes and the Local Multiframe Clock (LMFC)
          3. 6.3.9.4.3 Code Group Synchronization (CGS)
          4. 6.3.9.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 6.3.9.4.5 Frame and Multiframe Monitoring
        5. 6.3.9.5 64B/66B Link Layer
          1. 6.3.9.5.1 64B/66B Encoding
          2. 6.3.9.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
          3. 6.3.9.5.3 Block, Multiblock and Extended Multiblock Alignment using Sync Header
            1. 6.3.9.5.3.1 Cyclic Redundancy Check (CRC) Mode
            2. 6.3.9.5.3.2 Forward Error Correction (FEC) Mode
          4. 6.3.9.5.4 Initial Lane Alignment
          5. 6.3.9.5.5 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 6.3.9.6 Physical Layer
          1. 6.3.9.6.1 SerDes Pre-Emphasis
        7. 6.3.9.7 JESD204C Enable
        8. 6.3.9.8 Multi-Device Synchronization and Deterministic Latency
        9. 6.3.9.9 Operation in Subclass 0 Systems
      10. 6.3.10 Alarm Monitoring
        1. 6.3.10.1 Clock Upset Detection
        2. 6.3.10.2 FIFO Upset Detection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Dual-Channel Mode
      2. 6.4.2 Single-Channel Mode (DES Mode)
      3. 6.4.3 Dual-Input Single-Channel Mode (DUAL DES Mode)
      4. 6.4.4 JESD204C Modes
        1. 6.4.4.1 JESD204C Operating Modes Table
        2. 6.4.4.2 JESD204C Modes continued
        3. 6.4.4.3 JESD204C Transport Layer Data Formats
        4. 6.4.4.4 64B/66B Sync Header Stream Configuration
        5. 6.4.4.5 Dual DDC and Redundant Data Mode
      5. 6.4.5 Power-Down Modes
      6. 6.4.6 Test Modes
        1. 6.4.6.1 Serializer Test-Mode Details
        2. 6.4.6.2 PRBS Test Modes
        3. 6.4.6.3 Clock Pattern Mode
        4. 6.4.6.4 Ramp Test Mode
        5. 6.4.6.5 Short and Long Transport Test Mode
          1. 6.4.6.5.1 Short Transport Test Pattern
        6. 6.4.6.6 D21.5 Test Mode
        7. 6.4.6.7 K28.5 Test Mode
        8. 6.4.6.8 Repeated ILA Test Mode
        9. 6.4.6.9 Modified RPAT Test Mode
      7. 6.4.7 Calibration Modes and Trimming
        1. 6.4.7.1 Foreground Calibration Mode
        2. 6.4.7.2 Background Calibration Mode
        3. 6.4.7.3 Low-Power Background Calibration (LPBG) Mode
      8. 6.4.8 Offset Calibration
      9. 6.4.9 Trimming
    5. 6.5 Programming
      1. 6.5.1 Using the Serial Interface
        1. 6.5.1.1 SCS
        2. 6.5.1.2 SCLK
        3. 6.5.1.3 SDI
        4. 6.5.1.4 SDO
        5. 6.5.1.5 Streaming Mode
    6. 6.6 SPI Register Map
  8. 7 Application Information Disclaimer
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Wideband RF Sampling Receiver
        1. 7.2.1.1 Design Requirements
          1. 7.2.1.1.1 Input Signal Path
          2. 7.2.1.1.2 Clocking
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Calculating Values of AC-Coupling Capacitors
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Reconfigurable Dual-Channel 5GSPS or Single-Channel 10-Gsps Oscilloscope
        1. 7.2.2.1 Design Requirements
          1. 7.2.2.1.1 Input Signal Path
          2. 7.2.2.1.2 Clocking
          3. 7.2.2.1.3 ADC12DJ5200RF Ososcilloscope Applications
        2. 7.2.2.2 Application Curves
    3. 7.3 Initialization Set Up
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 Power Sequencing
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 静电放电警告
    7. 8.7 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
  12. 重要声明
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Data Sheet

ADC12DJ5200RF 10.4GSPS 单通道或 5.2GSPS 双通道 12 位射频采样模数转换器 (ADC)

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

下载最新的英语版本

1 特性

  • ADC 内核：
    • 12 位分辨率
    • 单通道模式下的采样率高达 10.4GSPS
    • 双通道模式下的采样率高达 5.2GSPS
  • 性能规格：
    • 本底噪声（–20dBFS，VFS = 1VPP-DIFF）：
      • 双通道模式： –151.8dBFS/Hz
      • 单通道模式： –154.4dBFS/Hz
    • ENOB（双通道，FIN = 2.4GHz）：8.6 位
  • VCMI 为 0V 时的缓冲模拟输入：
    • 模拟输入带宽 (-3dB)：8GHz
    • 可用输入频率范围：> 10GHz
    • 满量程输入电压（VFS，默认值）：0.8VPP
  • 无噪声孔径延迟 (tAD) 调节：
    • 精确采样控制：19fs 步长
    • 简化同步和交错
    • 温度和电压不变延迟
  • 简便易用的同步特性：
    • 自动 SYSREF 计时校准
    • 样片标记时间戳
  • JESD204C 串行数据接口：
    • 最大通道速率：17.16Gbps
    • 支持 64b/66b 和 8b/10b 编码
    • 8b/10b 模式兼容 JESD204B
  • 可选数字下变频器 (DDC)：
    • 4 倍、8 倍、16 倍和 32 倍复杂抽取
    • 每个 DDC 均具有四个独立的 32 位 NCO
  • 峰值射频输入功率 (Diff)：+26.5dBm（+27.5dBFS，560x 满量程功率）
  • 可实现均衡的可编程 FIR 滤波器
  • 功耗：4W
  • 电源：1.1V、1.9V

2 应用

  • 示波器和宽带数字转换器
  • 通信测试仪（802.11ad，5G）
  • 电子战（信号情报、电子情报）
  • 卫星通信 (SATCOM)
  • 射频采样软件定义无线电 (SDR)
  • 光谱测量

3 说明

ADC12DJ5200RF 器件是一款射频采样千兆采样模数转换器 (ADC)，可对从直流到 10GHz 以上的输入频率进行直接采样。ADC12DJ5200RF 可配置为双通道 5.2GSPS ADC 或单通道 10.4GSPS ADC。支持高达 10GHz 的可用输入频率范围，可对频率捷变系统的 L、S、C 和 X 频带进行直接射频采样。

ADC12DJ5200RF 使用具有多达 16 个串行通道的高速 JESD204C 输出接口，支持高达 17.16Gbps 的线路速率。通过 JESD204C 子类 1 支持确定性延迟和多器件同步。JESD204C 接口可进行配置，对线路速率和通道数进行权衡。支持 8b/10b 和 64b/66b 数据编码方案。64b/66b 编码支持前向纠错 (FEC)，可改进误码率。此接口向后兼容 JESD204B 接收器。

无噪声孔径延迟调节和 SYSREF 窗口等创新的同步特性可简化多通道应用的系统设计。提供可选的数字下变频器 (DDC)，以便将数字信号频谱下变频到基带信号并降低接口速率。可编程 FIR 滤波器可实现片上均衡。

封装信息
器件型号 封装(1) 封装尺寸(2)
ADC12DJ5200RF FCBGA (144) 10mm × 10mm
(1) 有关更多信息，请参阅节 10。
(2) 封装尺寸（长 × 宽）为标称值，并包括引脚（如适用）。
ADC12DJ5200RF ADC12DJ5200RF 方框图ADC12DJ5200RF 方框图

4 Pin Configuration and Functions

ADC12DJ5200RF AAV Package, 144-Ball Flip Chip BGATop View Figure 4-1 AAV Package, 144-Ball Flip Chip BGA
Top View
Table 4-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
AGND A1, A2, A3, A6, A7, B2, B3, B4, B5, B6, B7, C6, D1, D6, E1, E6, F2, F3, F6, G2, G3, G6, H1, H6, J1, J6, L2, L3, L4, L5, L6, L7, M1, M2, M3, M6, M7 — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
BG C3 O Band-gap voltage output. This pin is capable of sourcing only small currents and driving limited capacitive loads, as specified in the Recommended Operating Conditions table. This pin can be left disconnected if not used.
CALSTAT F7 O Foreground calibration status output or device alarm output. Functionality is programmed through CAL_STATUS_SEL. This pin can be left disconnected if not used.
CALTRIG E7 I Foreground calibration trigger input. This pin is only used if hardware calibration triggering is selected in CAL_TRIG_EN, otherwise software triggering is performed using CAL_SOFT_TRIG. Tie this pin to GND if not used.
CLK+ F1 I Device (sampling) clock positive input. The clock signal is strongly recommended to be AC-coupled to this input for best performance. In single-channel mode, the analog input signal is sampled on both the rising and falling edges. In dual-channel mode, the analog signal is sampled on the rising edge. This differential input has an internal untrimmed 100-Ω differential termination and is self-biased to the optimal input common-mode voltage as long as DEVCLK_LVPECL_EN is set to 0.
CLK– G1 I Device (sampling) clock negative input. TI strongly recommends using AC-coupling for best performance.
DA0+ E12 O High-speed serialized data output for channel A, lane 0, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DA0– F12 O High-speed serialized data output for channel A, lane 0, negative connection. This pin can be left disconnected if not used.
DA1+ C12 O High-speed serialized data output for channel A, lane 1, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DA1– D12 O High-speed serialized data output for channel A, lane 1, negative connection. This pin can be left disconnected if not used.
DA2+ A10 O High-speed serialized-data output for channel A, lane 2, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DA2– A11 O High-speed serialized-data output for channel A, lane 2, negative connection. This pin can be left disconnected if not used.
DA3+ A8 O High-speed serialized-data output for channel A, lane 3, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DA3– A9 O High-speed serialized-data output for channel A, lane 3, negative connection. This pin can be left disconnected if not used.
DA4+ E11 O High-speed serialized data output for channel A, lane 4, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DA4– F11 O High-speed serialized data output for channel A, lane 4, negative connection. This pin can be left disconnected if not used.
DA5+ C11 O High-speed serialized data output for channel A, lane 5, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DA5– D11 O High-speed serialized data output for channel A, lane 5, negative connection. This pin can be left disconnected if not used.
DA6+ B10 O High-speed serialized data output for channel A, lane 6, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DA6– B11 O High-speed serialized data output for channel A, lane 6, negative connection. This pin can be left disconnected if not used.
DA7+ B8 O High-speed serialized data output for channel A, lane 7, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DA7– B9 O High-speed serialized data output for channel A, lane 7, negative connection. This pin can be left disconnected if not used.
DB0+ H12 O High-speed serialized data output for channel B, lane 0, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DB0– G12 O High-speed serialized data output for channel B, lane 0, negative connection. This pin can be left disconnected if not used.
DB1+ K12 O High-speed serialized data output for channel B, lane 1, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DB1– J12 O High-speed serialized data output for channel B, lane 1, negative connection. This pin can be left disconnected if not used.
DB2+ M10 O High-speed serialized data output for channel B, lane 2, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DB2– M11 O High-speed serialized data output for channel B, lane 2, negative connection. This pin can be left disconnected if not used.
DB3+ M8 O High-speed serialized data output for channel B, lane 3, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DB3– M9 O High-speed serialized data output for channel B, lane 3, negative connection. This pin can be left disconnected if not used.
DB4+ H11 O High-speed serialized data output for channel B, lane 4, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DB4– G11 O High-speed serialized data output for channel B, lane 4, negative connection. This pin can be left disconnected if not used.
DB5+ K11 O High-speed serialized data output for channel B, lane 5, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DB5– J11 O High-speed serialized data output for channel B, lane 5, negative connection. This pin can be left disconnected if not used.
DB6+ L10 O High-speed serialized data output for channel B, lane 6, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DB6– L11 O High-speed serialized data output for channel B, lane 6, negative connection. This pin can be left disconnected if not used.
DB7+ L8 O High-speed serialized data output for channel B, lane 7, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DB7– L9 O High-speed serialized data output for channel B, lane 7, negative connection. This pin can be left disconnected if not used.
DGND A12, B12, D9, D10, F9, F10, G9, G10, J9, J10, L12, M12 — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
INA+ A4 I Channel A analog input positive connection. INA± is recommended for use in single channel mode for optimal performance. The differential full-scale input voltage is determined by the FS_RANGE_A register (see the Full-Scale Voltage (VFS) Adjustment section). This input is terminated to ground through a 50-Ω termination resistor. The input common-mode voltage is typically be set to 0 V (GND) and must follow the recommendations in the Recommended Operating Conditions table. This pin can be left disconnected if not used.
INA– A5 I Channel A analog input negative connection. INA± is recommended for use in single channel mode for optimal performance. See INA+ (pin A4) for detailed description. This input is terminated to ground through a 50-Ω termination resistor. This pin can be left disconnected if not used.
INB+ M4 I Channel B analog input positive connection. INA± is recommended for use in single channel mode for optimal performance. The differential full-scale input voltage is determined by the FS_RANGE_B register (see the Full-Scale Voltage (VFS) Adjustment section). This input is terminated to ground through a 50-Ω termination resistor. The input common-mode voltage must typically be set to 0 V (GND) and must follow the recommendations in the Recommended Operating Conditions table. This pin can be left disconnected if not used.
INB– M5 I Channel B analog input negative connection. INA± is recommended for use in single channel mode for optimal performance. See INB+ for detailed description. This input is terminated to ground through a 50-Ω termination resistor. This pin can be left disconnected if not used.
NCOA0 C7 I

LSB of NCO selection control for DDC A. NCOA0 and NCOA1 select which NCO, of a possible four NCOs, is used for digital mixing when using a complex output JMODE. The remaining unselected NCOs continue to run to maintain phase coherency and can be swapped in by changing the values of NCOA0 and NCOA1 (when CMODE = 1). This pin is an asynchronous input. See the NCO Fast Frequency Hopping (FFH) and NCO Selection sections for more information. Tie this pin to GND if not used.
NCOA1 D7 I

MSB of NCO selection control for DDC A. Tie this pin to GND if not used.
NCOB0 K7 I

LSB of NCO selection control for DDC B. NCOB0 and NCOB1 select which NCO, of a possible four NCOs, is used for digital mixing when using a complex output JMODE. The remaining unselected NCOs continue to run to maintain phase coherency and can be swapped in by changing the values of NCOB0 and NCOB1 (when CMODE = 1). This pin is an asynchronous input. See the NCO Fast Frequency Hopping (FFH) and NCO Selection sections for more information. Tie this pin to GND if not used.
NCOB1 J7 I

MSB of NCO selection control for DDC B. Tie this pin to GND if not used.
ORA0 C8 O Fast overrange detection status for channel A for the OVR_T0 threshold. When the analog input exceeds the threshold programmed into OVR_T0, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. This pin can be left disconnected if not used.
ORA1 D8 O Fast overrange detection status for channel A for the OVR_T1 threshold. When the analog input exceeds the threshold programmed into OVR_T1, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. This pin can be left disconnected if not used.
ORB0 K8 O Fast overrange detection status for channel B for the OVR_T0 threshold. When the analog input exceeds the threshold programmed into OVR_T0, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. This pin can be left disconnected if not used.
ORB1 J8 O Fast overrange detection status for channel B for the OVR_T1 threshold. When the analog input exceeds the threshold programmed into OVR_T1, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. This pin can be left disconnected if not used.
PD K6 I This pin disables all analog circuits and serializer outputs when set high for temperature diode calibration or to reduce power consumption when the device is not being used. Tie this pin to GND if not used.
SCLK F8 I Serial interface clock. This pin functions as the serial-interface clock input that clocks the serial programming data in and out. The Using the Serial Interface section describes the serial interface in more detail. Supports 1.1-V and 1.8-V CMOS levels.
SCS E8 I Serial interface chip select active low input. The Using the Serial Interface section describes the serial interface in more detail. Supports 1.1-V and 1.8-V CMOS levels. This pin has a 82-kΩ pullup resistor to VD11.
SDI G8 I Serial interface data input. The Using the Serial Interface section describes the serial interface in more detail. Supports 1.1-V and 1.8-V CMOS levels.
SDO H8 O Serial interface data output. The Using the Serial Interface section describes the serial interface in more detail. This pin is high impedance during normal device operation. This pin outputs 1.9-V CMOS levels during serial interface read operations. This pin can be left disconnected if not used.
SYNCSE C2 I Single-ended JESD204C SYNC signal. This input is an active low input that is used to initialize the JESD204C serial link in 8B/10B modes when SYNC_SEL is set to 0. The 64B/66B modes do not use the SYNC signal for initialization, however it may be used for NCO synchronization. When toggled low in 8B/10B modes this input initiates code group synchronization (see the Code Group Synchronization (CGS) section). After code group synchronization, this input must be toggled high to start the initial lane alignment sequence (see the Initial Lane Alignment Sequence (ILAS) section). A differential SYNC signal can be used instead by setting SYNC_SEL to 1 and using TMSTP± as a differential SYNC input. Tie this pin to GND if differential SYNC (TMSTP±) is used as the JESD204C SYNC signal.
SYSREF+ K1 I The SYSREF positive input is used to achieve synchronization and deterministic latency across the JESD204C interface. This differential input (SYSREF+ to SYSREF–) has an internal untrimmed 100-Ω differential termination and can be AC-coupled when SYSREF_LVPECL_EN is set to 0. This input is self-biased when SYSREF_LVPECL_EN is set to 0. The termination changes to 50 Ω to ground on each input pin (SYSREF+ and SYSREF–) and can be DC-coupled when SYSREF_LVPECL_EN is set to 1. This input is not self-biased when SYSREF_LVPECL_EN is set to 1 and must be biased externally to the input common-mode voltage range provided in the Recommended Operating Conditions table.
SYSREF– L1 I SYSREF negative input
TDIODE+ K2 I Temperature diode positive (anode) connection. An external temperature sensor can be connected to TDIODE+ and TDIODE– to monitor the junction temperature of the device. This pin can be left disconnected if not used.
TDIODE– K3 I Temperature diode negative (cathode) connection. This pin can be left disconnected if not used.
TMSTP+ B1 I Timestamp input positive connection or differential JESD204C SYNC positive connection. This input is a timestamp input, used to mark a specific sample, when TIMESTAMP_EN is set to 1. This differential input is used as the JESD204C SYNC signal input when SYNC_SEL is set 1. This input can be used as both a timestamp and differential SYNC input at the same time, allowing feedback of the SYNC signal using the timestamp mechanism. TMSTP± uses active low signaling when used as a JESD204C SYNC. For additional usage information, see the Timestamp section.
TMSTP_RECV_EN must be set to 1 to use this input. This differential input (TMSTP+ to TMSTP–) has an internal untrimmed 100-Ω differential termination and can be AC-coupled when TMSTP_LVPECL_EN is set to 0. The termination changes to 50 Ω to ground on each input pin (TMSTP+ and TMSTP–) and can be DC coupled when TMSTP_LVPECL_EN is set to 1. This pin is not self-biased and therefore must be externally biased for both AC- and DC-coupled configurations. The common-mode voltage must be within the range provided in the Recommended Operating Conditions table when both AC and DC coupled. This pin can be left disconnected and disabled (TMSTP_RECV_EN = 0) if SYNCSE is used for JESD204C SYNC and timestamp is not required.
TMSTP– C1 I Timestamp input positive connection or differential JESD204C SYNC negative connection. This pin can be left disconnected and disabled (TMSTP_RECV_EN = 0) if SYNCSE is used for JESD204C SYNC and timestamp is not required.
VA11 C5, D2, D3, D5, E5, F5, G5, H5, J2, J3, J5, K5 I 1.1-V analog supply
VA19 C4, D4, E2, E3, E4, F4, G4, H2, H3, H4, J4, K4 I 1.9-V analog supply
VD11 C9, C10, E9, E10, G7, H7, H9, H10, K9, K10 I 1.1-V digital supply

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VDD Supply voltage range VA19(2) –0.3 2.35 V
VA11(2) –0.3 1.32
VD11(3) –0.3 1.32
Voltage between VD11 and VA11 –1.32 1.32
VGND Voltage between AGND and DGND –0.1 0.1 V
VPIN Pin voltage range DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–, TMSTP+, TMSTP–(3) –0.5 VD11 + 0.5(5) V
CLK+, CLK–, SYSREF+, SYSREF–(2) –0.5 VA11 + 0.5(4)
BG, TDIODE+, TDIODE–(2) –0.5 VA19 + 0.5(6)
INA+, INA–, INB+, INB–(2) –1 1
CALSTAT, CALTRIG, NCOA0, NCOA1, NCOB0, NCOB1, ORA0, ORA1, ORB0, ORB1, PD, SCLK, SCS, SDI, SDO, SYNCSE(2) –0.5 VA19 + 0.5(6)
IMAX(ANY) Peak input current (any input except INA+, INA–, INB+, INB–) –25 25 mA
IMAX(INx) Peak input current (INA+, INA–, INB+, INB–) –50 50 mA
PMAX(INx) Peak RF input power (INA+, INA–, INB+, INB–) differential with ZS-DIFF = 100 Ω, up to 21 days(7) 26.5 dBm
Single-ended with ZS-SE = 50 Ω 16.4 dBm
IMAX(ALL) Peak total input current (sum of absolute value of all currents forced in or out, not including power-supply current) 100 mA
Tj Junction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions . Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Measured to AGND.
(3) Measured to DGND.
(4) Maximum voltage not to exceed VA11 absolute maximum rating.
(5) Maximum voltage not to exceed VD11 absolute maximum rating.
(6) Maximum voltage not to exceed VA19 absolute maximum rating.
(7) Tested continuously for 21 days with FIN = 1.2GHz on a typical device. At the end of testing, the device was not damaged. During the overdrive, the ADC is still properly converting the input signal, although it will be saturated for voltages beyond the input fullscale.

5.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Supply voltage range VA19, analog 1.9-V supply(2) 1.8 1.9 2.0 V
VA11, analog 1.1-V supply(2) 1.05 1.1 1.15
VD11, digital 1.1-V supply(3) 1.05 1.1 1.15
VCMI Input common-mode voltage INA+, INA–, INB+, INB–(2) –50 0 100 mV
CLK+, CLK–, SYSREF+, SYSREF–(2)(4) 0 0.3 0.55 V
TMSTP+, TMSTP–(3)(5) 0 0.3 0.55
VID Input voltage, peak-to-peak differential CLK+ to CLK–, SYSREF+ to SYSREF–, TMSTP+ to TMSTP– 0.4 1.0 2.0 VPP-DIFF
INA+ to INA–, INB+ to INB– 0.8(6)
IC_TD Temperature diode input current TDIODE+ to TDIODE– 100 µA
CL BG maximum load capacitance 50 pF
IO BG maximum output current 100 µA
DC Input clock duty cycle 30 50 70 %
TA Operating free-air temperature –40 85 °C
TJ Operating junction temperature 125(1) °C
(1) Prolonged use above junction temperature of 105°C may increase the device failure-in-time (FIT) rate.
(2) Measured to AGND.
(3) Measured to DGND.
(4) TI strongly recommends that CLK± be AC-coupled with DEVCLK_LVPECL_EN set to 0 to allow CLK± to self-bias to the optimal input common-mode voltage for best performance. TI recommends AC-coupling for SYSREF± unless DC-coupling is required, in which case, the LVPECL input mode must be used (SYSREF_LVPECL_EN = 1).
(5) TMSTP± does not have internal biasing that requires TMSTP± to be biased externally whether AC-coupled with TMSTP_LVPECL_EN = 0 or DC-coupled with TMSTP_LVPECL_EN= 1.
(6) The ADC output code saturates when VID for INA± or INB± exceeds the programmed full-scale voltage(VFS) set by FS_RANGE_A for INA± or FS_RANGE_B for INB±.

5.4 Thermal Information

THERMAL METRIC(1) ADC12DJ5200RF UNIT
AAV or ZEG (FCBGA)
144 PINS
RθJA Junction-to-ambient thermal resistance 23.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 0.8 °C/W
RθJB Junction-to-board thermal resistance 8.4 °C/W
ψJT Junction-to-top characterization parameter 0.23 °C/W
ψJB Junction-to-board characterization parameter 8.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

 
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