ZHCSH81 December 2017 PGA302
PRODUCTION DATA.
The device includes modules that verify that the output signal of each gain is within a certain range. This ensures that gain stages in the signal chain are working correctly. AVDD voltage is used to generate the thresholds voltages for comparison.
When a fault is detected, the corresponding bit in AFEDIAG register is set. Even after the faulty condition is removed, the fault bits will remain latched. To remove the fault, M0 software should read the fault bit and write a logic zero back to the bit. A system reset will clear the fault.