ZHCSH81
December 2017
PGA302
PRODUCTION DATA.
1
特性
2
应用
3
说明
Device Images
PGA302 简化框图
4
修订历史记录
5
说明 (续)
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Overvoltage and Reverse Voltage Protection
7.6
Linear Regulators
7.7
Internal Reference
7.8
Internal Oscillator
7.9
Bridge Sensor Supply
7.10
Temperature Sensor Supply
7.11
Bridge Offset Cancel
7.12
P Gain and T Gain Input Amplifiers (Chopper Stabilized)
7.13
Analog-to-Digital Converter
7.14
Internal Temperature Sensor
7.15
Bridge Current Measurement
7.16
One Wire Interface
7.17
DAC Output
7.18
DAC Gain for DAC Output
7.19
Non-Volatile Memory
7.20
Diagnostics - PGA30x
7.21
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Overvoltage and Reverse Voltage Protection
8.3.2
Linear Regulators
8.3.3
Internal Reference
8.3.4
Internal Oscillator
8.3.5
VBRGP and VBRGN Supply for Resistive Bridge
8.3.6
ITEMP Supply for Temperature Sensor
8.3.7
P Gain
8.3.8
T Gain
8.3.9
Bridge Offset Cancel
8.3.10
Analog-to-Digital Converter
8.3.10.1
Sigma Delta Modulator for ADC
8.3.10.2
Decimation Filter for ADC
8.3.10.3
Internal Temperature Sensor ADC Conversion
8.3.10.4
ADC Scan Mode
8.3.10.4.1
P-T Multiplexer Timing in Auto Scan Mode
8.3.11
Internal Temperature Sensor
8.3.12
Bridge Current Measurement
8.3.13
Digital Interface
8.3.14
OWI
8.3.14.1
Overview of OWI Interface
8.3.14.2
Activating and Deactivating the OWI Interface
8.3.14.2.1
Activating OWI Communication
8.3.14.2.2
Deactivating OWI Communication
8.3.14.3
OWI Protocol
8.3.14.3.1
OWI Frame Structure
8.3.14.3.1.1
Standard field structure:
8.3.14.3.1.2
Frame Structure
8.3.14.3.1.3
Sync Field
8.3.14.3.1.4
Command Field
8.3.14.3.1.5
Data Field(s)
8.3.14.3.2
OWI Commands
8.3.14.3.2.1
OWI Write Command
8.3.14.3.2.2
OWI Read Initialization Command
8.3.14.3.2.3
OWI Read Response Command
8.3.14.3.2.4
OWI Burst Write Command (EEPROM Cache Access)
8.3.14.3.2.5
OWI Burst Read Command (EEPROM Cache Access)
8.3.14.3.3
OWI Operations
8.3.14.3.3.1
Write Operation
8.3.14.3.3.2
Read Operation
8.3.14.3.3.3
EEPROM Burst Write
8.3.14.3.3.4
EEPROM Burst Read
8.3.14.4
OWI Communication Error Status
8.3.15
I2C Interface
8.3.15.1
Overview of I2C Interface
8.3.15.2
I2C Interface Protocol
8.3.15.3
Clocking Details of I2C Interface
8.3.16
DAC Output
8.3.17
DAC Gain for DAC Output
8.3.17.1
Connecting DAC Output to DAC GAIN Input
8.3.18
Memory
8.3.18.1
EEPROM Memory
8.3.18.1.1
EEPROM Cache
8.3.18.1.2
EEPROM Programming Procedure
8.3.18.1.3
EEPROM Programming Current
8.3.18.1.4
CRC
8.3.19
Diagnostics
8.3.19.1
Power Supply Diagnostics
8.3.19.2
Sensor Connectivity/Gain Input Faults
8.3.19.3
Gain Output Diagnostics
8.3.19.4
PGA302 Harness Open Wire Diagnostics
8.3.19.5
EEPROM CRC and TRIM Error
8.3.20
Digital Compensation and Filter
8.3.20.1
Digital Gain and Offset
8.3.20.2
TC and NL Correction
8.3.20.3
Clamping
8.3.20.4
Filter
8.3.21
Revision ID
8.4
Device Functional Modes
8.5
Register Maps
8.5.1
Programmer's Model
8.5.1.1
Memory Map
8.5.1.2
Control and Status Registers
8.5.1.2.1
MICRO_INTERFACE_CONTROL (DI Page Address = 0x0) (DI Page Offset = 0x0C)
Table 11.
MICRO_INTERFACE_CONTROL Register Field Descriptions
8.5.1.2.2
PSMON1 (M0 Address= 0x40000558) (DI Page Address = 0x2) (DI Page Offset = 0x58)
Table 12.
PSMON1 Register Field Descriptions
8.5.1.2.3
AFEDIAG (M0 Address= 0x4000055A) (DI Page Address = 0x2) (DI Page Offset = 0x5A)
Table 13.
AFEDIAG Register Field Descriptions
8.5.1.2.4
P_GAIN_SELECT (DI Page Address = 0x2) (DI Page Offset = 0x47)
Table 14.
P_GAIN_SELECT Register Field Descriptions
8.5.1.2.5
T_GAIN_SELECT (DI Page Address = 0x2) (DI Page Offset = 0x48)
Table 15.
T_GAIN_SELECT Register Field Descriptions
8.5.1.2.6
TEMP_CTRL (DI Page Address = 0x2) (DI Page Offset = 0x4C)
Table 16.
TEMP_CTRL Register Field Descriptions
8.5.1.2.7
OFFSET_CANCEL (DI Page Address = 0x2) (DI Page Offset = 0x4E)
Table 17.
OFFSET_CANCEL Register Field Descriptions
8.5.1.2.8
PADC_DATA1 (DI Page Address = 0x0) (DI Page Offset = 0x10)
Table 18.
PADC_DATA1 Register Field Descriptions
8.5.1.2.9
PADC_DATA2 (DI Page Address = 0x0) (DI Page Offset = 0x11)
Table 19.
PADC_DATA2 Register Field Descriptions
8.5.1.2.10
TADC_DATA1 (DI Page Address = 0x0) (DI Page Offset = 0x14)
Table 20.
TADC_DATA1 Register Field Descriptions
8.5.1.2.11
TADC_DATA2 (DI Page Address = 0x0) (DI Page Offset = 0x15)
Table 21.
TADC_DATA2 Register Field Descriptions
8.5.1.2.12
DAC_REG0_1 (DI Page Address = 0x2) (DI Page Offset = 0x30)
Table 22.
DAC_REG0_1 Register Field Descriptions
8.5.1.2.13
DAC_REG0_2 (DI Page Address = 0x2) (DI Page Offset = 0x31)
Table 23.
DAC_REG0_2 Register Field Descriptions
8.5.1.2.14
OP_STAGE_CTRL (DI Page Address = 0x2) (DI Page Offset = 0x3B)
Table 24.
OP_STAGE_CTRL Register Field Descriptions
8.5.1.2.15
EEPROM_ARRAY (DI Page Address = 0x5) (DI Page Offset = 0x00 - 0x7F)
Table 25.
EEPROM_ARRAY Register Range Descriptions
8.5.1.2.16
EEPROM_CACHE_BYTE0 (DI Page Address = 0x5) (DI Page Offset = 0x80)
Table 26.
EEPROM_CACHE_BYTE0 Register Field Descriptions
8.5.1.2.17
EEPROM_CACHE_BYTE1 (DI Page Address = 0x5) (DI Page Offset = 0x81)
Table 27.
EEPROM_CACHE_BYTE1 Register Field Descriptions
8.5.1.2.18
EEPROM_PAGE_ADDRESS (DI Page Address = 0x5) (DI Page Offset = 0x82)
Table 28.
EEPROM_PAGE_ADDRESS Register Field Descriptions
8.5.1.2.19
EEPROM_CTRL (DI Page Address = 0x5) (DI Page Offset = 0x83)
Table 29.
EEPROM_CTRL Register Field Descriptions
8.5.1.2.20
EEPROM_CRC (DI Page Address = 0x5) (DI Page Offset = 0x84)
Table 30.
EEPROM_CRC Register Field Descriptions
8.5.1.2.21
EEPROM_STATUS (DI Page Address = 0x5) (DI Page Offset = 0x85)
Table 31.
EEPROM_STATUS Register Field Descriptions
8.5.1.2.22
EEPROM_CRC_STATUS (DI Page Address = 0x5) (DI Page Offset = 0x86)
Table 32.
EEPROM_CRC_STATUS Register Field Descriptions
8.5.1.2.23
EEPROM_CRC_VALUE (DI Page Address = 0x5) (DI Page Offset = 0x87)
Table 33.
EEPROM_CRC_VALUE Register Field Descriptions
8.5.1.2.24
H0 (EEPROM Address= 0x40000000)
Table 34.
H0 Register Field Descriptions
8.5.1.2.25
H1 (EEPROM Address= 0x40000002)
Table 35.
H1 Register Field Descriptions
8.5.1.2.26
H2 (EEPROM Address= 0x40000004)
Table 36.
H2 Register Field Descriptions
8.5.1.2.27
H3 (EEPROM Address= 0x40000006)
Table 37.
H3 Register Field Descriptions
8.5.1.2.28
G0 (EEPROM Address= 0x40000008)
Table 38.
G0 Register Field Descriptions
8.5.1.2.29
G1 (EEPROM Address= 0x4000000A)
Table 39.
G1 Register Field Descriptions
8.5.1.2.30
G2 (EEPROM Address= 0x4000000C)
Table 40.
G2 Register Field Descriptions
8.5.1.2.31
G3 (EEPROM Address= 0x4000000E)
Table 41.
G3 Register Field Descriptions
8.5.1.2.32
N0 (EEPROM Address= 0x40000010)
Table 42.
N0 Register Field Descriptions
8.5.1.2.33
N1 (EEPROM Address= 0x40000012)
Table 43.
N1 Register Field Descriptions
8.5.1.2.34
N2 (EEPROM Address= 0x40000014)
Table 44.
N2 Register Field Descriptions
8.5.1.2.35
N3 (EEPROM Address= 0x40000016)
Table 45.
N3 Register Field Descriptions
8.5.1.2.36
M0 (EEPROM Address= 0x40000018)
Table 46.
M0 Register Field Descriptions
8.5.1.2.37
M1 (EEPROM Address= 0x4000001A)
Table 47.
M1 Register Field Descriptions
8.5.1.2.38
M2 (EEPROM Address= 0x4000001C)
Table 48.
M2 Register Field Descriptions
8.5.1.2.39
M3 (EEPROM Address= 0x4000001E)
Table 49.
M3 Register Field Descriptions
8.5.1.2.40
PADC_GAIN (EEPROM Address= 0x40000020)
Table 50.
PADC_GAIN Register Field Descriptions
8.5.1.2.41
TADC_GAIN (EEPROM Address= 0x40000021)
Table 51.
TADC_GAIN Register Field Descriptions
8.5.1.2.42
PADC_OFFSET (EEPROM Address= 0x40000022)
Table 52.
PADC_OFFSET Register Field Descriptions
8.5.1.2.43
TADC_OFFSET (EEPROM Address= 0x40000024)
Table 53.
TADC_OFFSET Register Field Descriptions
8.5.1.2.44
TEMP_SW_CTRL (EEPROM Address= 0x40000028)
Table 54.
TEMP_SW_CTRL Register Field Descriptions
8.5.1.2.45
DAC_FAULT_MSB (EEPROM Address= 0x4000002A)
Table 55.
DAC_FAULT_MSB Register Field Descriptions
8.5.1.2.46
LPF_A0_MSB (EEPROM Address= 0x4000002B)
Table 56.
LPF_A0_MSB Register Field Descriptions
8.5.1.2.47
LPF_A1 (EEPROM Address= 0x4000002C)
Table 57.
A1 Register Field Descriptions
8.5.1.2.48
LPF_A2 (EEPROM Address= 0x4000002E)
Table 58.
A2 Register Field Descriptions
8.5.1.2.49
.LPF_B1 (EEPROM Address= 0x40000030)
Table 59.
B1 Register Field Descriptions
8.5.1.2.50
NORMAL_LOW (EEPROM Address= 0x40000032)
Table 60.
NORMAL_LOW Register Field Descriptions
8.5.1.2.51
NORMAL_HIGH (EEPROM Address= 0x40000034)
Table 61.
NORMAL_HIGH Register Field Descriptions
8.5.1.2.52
LOW_CLAMP (EEPROM Address= 0x40000036)
Table 62.
LOW_CLAMP Register Field Descriptions
8.5.1.2.53
HIGH_CLAMP (EEPROM Address= 0x40000038)
Table 63.
HIGH_CLAMP Register Field Descriptions
8.5.1.2.54
DIAG_BIT_EN (EEPROM Address= 0x4000003A)
Table 64.
DIAG_BIT_EN Register Field Descriptions
9
Application and Implementation
9.1
Application Information
9.1.1
0-5V Voltage Output
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Application Data
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
器件和文档支持
12.1
接收文档更新通知
12.2
社区资源
12.3
商标
12.4
静电放电警告
12.5
Glossary
13
机械、封装和可订购信息
12
器件和文档支持