DATA SHEET
CC3220MODx 和 CC3220MODAx SimpleLink™ Wi-Fi® CERTIFIED™ 无线 MCU 模块
本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。
1 特性
- CC3220MODx 无线 MCU 模块系列，包含 SimpleLink™Wi-Fi® 单芯片无线 MCU - CC3220MODS 和 CC3220MODAS 模块包含 CC3220SM2ARGK 无线 MCU；CC3220MODSF 和 CC3220MODASF 模块包含 CC3220SF12ARGK 无线 MCU。完全集成的工业温度级绿色模块，包括所有必需的时钟、SPI 闪存和无源器件
- CC3220MODAx 模块包含一体化天线，可轻松集成到主机系统中
- CC3220MODx 和 CC3220MODAx SimpleLink™ Wi-Fi® 无线 MCU 片上系统 (SoC) 包含支持两种独立执行环境的单芯片：
- 用户应用专用的 Arm®Cortex®-M4 MCU
- 用以运行所有 Wi-Fi 和互联网逻辑层的网络处理器 MCU
- 获得 FCC、IC、CE、MIC 和 SRRC 认证
- Wi-Fi Alliance 成员可以申请 Wi-Fi CERTIFIED™ 模块的证书转让
- 1.27mm 间距 QFM 封装，实现轻松组装和低成本 PCB 设计
- 应用 MCU 子系统：
- Arm® Cortex®-M4 内核，运行频率 80MHz
- 嵌入式存储器：
- CC3220MODS 和 CC3220MODAx 型号包含 256KB RAM
- CC3220MODSF 和 CC3220MODASF 是基于闪存的 MCU，集成 1MB 闪存和 256KB RAM
- 采用 ROM 的外设驱动器
- McASP 支持两个 I2S 通道
- SD
- SPI
- I2C
- UART
- 8 位同步图像接口
- 4 个具有 16 位 PWM
模式的通用计时器 (GPT) - 1 个看门狗计时器模块
- 4 通道、12 位模数转换器 (ADC)
- 调试接口：JTAG、cJTAG 和 SWD
- Wi-Fi 网络处理器子系统：
- Wi-Fi®Internet-on-a chip™ 专用 Arm® MCU 可将 Wi-Fi 和互联网协议完全从应用 MCU 中转移
- Wi-Fi® 模式：
- 802.11b/g/n 基站
- 802.11b/g/n 接入点支持多达 4 个基站
- Wi-Fi Direct® 客户端和组所有者
- WPA2™ 个人版和企业版安全性：WEP、WPA™、WPA2 PSK 和 WPA2 企业版 (802.1x)、WPA3™ 个人版和企业版
- IPv4 和 IPv6 TCP 与 IP 堆栈
- 业界通用 BSD 套接字应用编程接口 (API)：
- 16 个同步 TCP 或 UDP 套接字
- 6 个同步 TLS 和 SSL 套接字
- IP 寻址：具有重复地址检测 (DAD) 的 StaticIP、LLA、DHCPv4、DHCPv6
- SimpleLink™ 技术连接管理器，可实现自主快速的 Wi-Fi 连接
- 可通过 SmartConfig™ 技术、AP 模式和 WPS2 选项灵活配置 Wi-Fi
- RESTful API 支持（使用内部 HTTP 服务器）
- 在专用网络处理器上运行的嵌入式网络应用
- 广泛的安全特性：
- 硬件特性：
- 独立执行环境
- 器件身份
- 用于实现高级快速安全性的硬件加密引擎，其中包括：AES、DES、3DES、SHA2、MD5、CRC 和校验和
- 初始安全编程：
- 调试安全性
- JTAG 和调试端口处于锁定状态
- 个人和企业 Wi-Fi 安全性
- 安全套接字
（SSLv3、TLS1.0、TLS1.1、TLS1.2）
- 硬件特性：
- 网络安全性
- HTTPS 服务器
- 受信任的根证书目录
- TI 信任根公钥
- SW IP 保护：
- 安全密钥存储
- 文件系统安全性
- 软件篡改检测
- 克隆保护
- 安全启动：启动期间验证运行时二进制的完整性和真实性
- 在专用网络处理器上运行的嵌入式网络应用：
- 具有动态用户回调的 HTTP 和 HTTPS 网络服务器
- mDNS、DNS-SD 和 DHCP 服务器
- Ping
- 恢复机制：可恢复到出厂默认设置或恢复到完整出厂映像
- Wi-Fi TX 功率：
- 1 DSSS 时为 17.0dBm
- 54 OFDM 时为 13.5dBm
- Wi-Fi RX 灵敏度：
- 1 DSSS 时为 –95.0dBm
- 54 OFDM 时为 –73.5dBm
- 应用吞吐量：
- UDP：16Mbps
- TCP：13Mbps
- 电源管理子系统：
- 具有宽电源电压范围的
集成式直流/直流转换器- VBAT：2.3V 至 3.6V
- 高级低功耗模式：
- 关断：1µA
- 休眠：5µA
- 低功耗深度睡眠 (LPDS)：135µA（测试对象为具有 256KB RAM 容量的 CC3220MODS 和 CC3220MODSF）
- RX 流量（MCU 处于活动模式）：54 OFDM 时为 59mA（测试对象为 CC3220MODS；CC3220MODSF 和 CC3220MODASF 会额外消耗
15mA） - TX 流量（MCU 处于活动模式）：在 54 OFDM、最大功耗时为 223mA（测试对象为 CC3220MODS；CC3220MODSF 和 CC3220MODASF 会额外消耗
15mA） - 空闲连接（MCU 处于 LPDS 状态）：DTIM = 1 时为 710µA（测试对象为具有 256KB RAM 容量的 CC3220MODS 和 CC3220MODSF）
- 具有宽电源电压范围的
- 其他集成元件：
- 40.0MHz 晶体
- 32.768kHz 晶体 (RTC)
- 32 兆位 SPI 串行闪存
- 射频滤波器和无源器件
- 尺寸兼容的 QFM 封装：
- CC3220MODx：1.27mm 间距、
63 引脚、20.5mm × 17.5mm - CC3220MODAx：1.27mm 间距、
63 引脚、20.5mm × 25.0mm
- CC3220MODx：1.27mm 间距、
- 工作温度：
- 环境温度范围：–40°C 至 +85°C
- 模块支持 SimpleLink 开发人员生态系统
3 说明
使用此完全可编程的无线微控制器 (MCU) 模块开始您的设计，它经过 FCC、IC、CE、MIC 和 SRRC 认证，且具有内置 Wi-Fi 连接。德州仪器 (TI)™ 的 SimpleLink™ CC3220MODx 和 CC3220MODAx 模块系列专为物联网而设计，是集成了两个物理隔离片上 MCU 的无线模块。
- 应用处理器 Arm® Cortex®-M4 MCU 具有用户专用的 256KB RAM（CC3220SF 型号上具有 1MB XIP 闪存）。
- 一个网络处理器 MCU，可运行所有 Wi-Fi® 和互联网逻辑层。此基于 ROM 的子系统包含 802.11b/g/n 无线电、基带和具有强大加密引擎的 MAC，采用 256 位加密，可实现快速安全的互联网连接。
CC3220MODx 和 CC3220MODAx 无线 MCU 系列属于 TI 第二代 Internet-on-a chip™ 系列解决方案。这一代引进了可进一步简化互联网连接的新特性和功能。新功能包括：
- IPv6
- 增强的 Wi-Fi 配置
- 优化的低功耗管理
- 增强的文件系统安全
- Wi-Fi AP 可连接多达 4 个基站
- 可同时打开更多的 BSD 套接字—多达 16 个 BSD 套接字（其中 6 个支持安全型 HTTPS）
- 支持 HTTPS
- 支持 RESTful API
- 非对称密钥加密库
电源管理子系统包括支持宽电源电压范围的集成式直流/直流转换器。此子系统支持低功耗深度睡眠、RTC 休眠（仅消耗 5µA）和关断模式（仅消耗
1µA）等低功耗模式，有助于延长电池寿命。
该模块包含多种外设，如快速并行摄像头接口、I2S、SD、UART、SPI、I2C 和 4 通道 ADC。
SimpleLink CC3220MODx 和 CC3220MODAx 模块系列有 4 个不同的模块型号：CC3220MODS、CC3220MODSF、CC3220MODA 和 CC3220MODASF。
- CC3220MODS 和 CC3220MODAS 模块包含用于处理代码和数据的应用专用型嵌入式 RAM (256KB)。此外，CC3220MODAS 还包含一体式天线。
- CC3220MODSF 和 CC3220MODASF 模块包含用于处理代码和数据的应用专用型串行闪存 (1MB) 和 RAM (256KB)。此外，CC3220MODASF 还包含一体式天线。
这 4 个模块集成有 40MHz 晶体、32.768kHz RTC 时钟、32Mb SPI 串行闪存、射频滤波器和无源器件。这些模块还具有其他安全功能，例如经过加密和身份验证的文件系统、用户 IP 加密和身份验证、安全引导（闪存引导时对应用映像进行身份验证和完整性验证）等。
CC3220MODx 和 CC3220MODAx 器件是 SimpleLink™ MCU 平台的一部分，包含 Wi-Fi、低功耗蓝牙®、低于 1GHz 和主机 MCU。它们都共用配有单核软件开发套件 (SDK) 和丰富工具集的通用、易用型开发环境。一次性集成 SimpleLink 平台后，用户可以将产品组合中器件的任何组合添加至您的设计中。SimpleLink 平台的最终目标是确保设计要求变更时，完全重复使用代码。
CC3220MODx 和 CC3220MODAx 模块系列是完整的平台解决方案，其中包括软件、示例应用、工具、用户和编程指南、参考设计以及 E2E™ 在线社区。该模块系列还是 SimpleLink™ MCU 产品系列的一部分，并且支持 SimpleLink™ 开发人员生态系统。如需了解更多相关信息，请访问 www.ti.com.cn/simplelink/cn。
器件信息(1)
| 器件型号 | 封装 | 封装尺寸（标称值） |
|---|---|---|
| CC3220MODSM2MOBR | QFM (63) | 20.50mm × 17.50mm |
| CC3220MODSF12MOBR | QFM (63) | 20.50mm × 17.50mm |
| CC3220MODASM2MONR | QFM (63) | 25.50mm × 20.50mm |
| CC3220MODASF12MONR | QFM (63) | 25.50mm × 20.50mm |
(1) 有关详细信息，请参阅 Section 13。
4 功能方框图
图 4-1 显示了 CC3220MODx 模块的功能方框图。
图 4-1 CC3220MODx 功能方框图图 4-2 显示了 CC3220MODAx 模块的功能方框图。
图 4-2 CC3220MODAx 功能方框图有关 3200MOD 模块引脚多路复用的详细信息，请参阅 CC3200 SimpleLink™ Wi-Fi® 无线和物联网解决方案，单芯片无线 MCU 数据表。
图 4-3 CC3200MOD 模块功能方框图图 4-4 显示了 CC3220x 硬件概述。
图 4-4 CC3220x 硬件概述图 4-5 显示了 CC3220x 嵌入式软件的概述。
图 4-5 CC3220x 嵌入式软件概述5 Revision History
Changes from September 22, 2020 to May 13, 2021 (from Revision D (September 2020) to Revision E (May 2021))
- Section 1 新增了 WPA3 个人版和企业版Go
- 更新了整个文档中的表格、图和交叉参考的编号格式Go
- Section 3新增了 WPA3 个人版和企业版Go
- Added WPA3 personal and enterprise to Table 6-1 Go
- Added WPA3 personal and enterprise to Section 9.3 Go
- Added WPA3 Personal and WPA3 Enterprise to Section 9.3.1 Go
- Added WPA3 personal and enterprise to Table 9-1 Go
- Added CC3220MODA reel information in Section 13.2 Go
6 Device Comparison
Table 6-1 shows the features supported across different CC3x20 modules.
Table 6-1 Device Features
Comparison
| FEATURE | DEVICE | ||||
|---|---|---|---|---|---|
| CC3120MOD | CC3220MODS | CC3220MODSF | CC3220MODAS | CC3220MODASF | |
| On-board chip | CC3120 | CC3220S | CC3220SF | CC3220S | CC3220SF |
| On-board ANT | No | No | No | Yes | Yes |
| sFlash | 32-Mbit | 32-Mbit | 32-Mbit | 32-Mbit | 32-Mbit |
| Regulatory certifications | FCC, IC, CE, MIC, SRRC | FCC, IC, CE, MIC, SRRC | FCC, IC, CE, MIC, SRRC | FCC, IC, CE, MIC, SRRC | FCC, IC, CE, MIC, SRRC |
| Wi-Fi Alliance® Certification | Yes | Yes | Yes | Yes | Yes |
| Input voltage | 2.3 V to 3.6 V | 2.3 V to 3.6 V | 2.3 V to 3.6 V | 2.3 V to 3.6 V | 2.3 V to 3.6 V |
| Package | 17.5 mm × 20.5 mm QFM | 17.5 mm × 20.5 mm QFM | 17.5 mm × 20.5 mm QFM | 25.0 mm × 20.5 mm QFM | 25.0 mm × 20.5 mm QFM |
| Operating temperature range | –40°C to +85°C | –40°C to +85°C | –40°C to +85°C | –40°C to +85°C | –40°C to +85°C |
| Classification | Wi-Fi Network Processor | Wireless Microcontroller | Wireless Microcontroller | Wireless Microcontroller | Wireless Microcontroller |
| Standard | 802.11 b/g/n | 802.11 b/g/n | 802.11 b/g/n | 802.11 b/g/n | 802.11 b/g/n |
| Frequency | 2.4 GHz | 2.4 GHz | 2.4 GHz | 2.4 GHz | 2.4 GHz |
| TCP/IP Stack | IPv4, IPv6 | IPv4, IPv6 | IPv4, IPv6 | IPv4, IPv6 | IPv4, IPv6 |
| Sockets | 16 | 16 | 16 | 16 | 16 |
| Integrated MCU | – | Arm® Cortex®-M4 at 80 MHz | Arm® Cortex®-M4 at 80 MHz | Arm® Cortex®-M4 at 80 MHz | Arm® Cortex®-M4 at 80 MHz |
| ON-CHIP APPLICATION MEMORY | |||||
| RAM | – | 256KB | 256KB | 256KB | 256KB |
| Flash | – | – | 1MB | – | 1MB |
| PERIPHERALS AND INTERFACES | |||||
| Universal Asynchronous Receiver/Transmitter (UART) |
1 | 2 | 2 | 2 | 2 |
| Serial Port Interface (SPI) | 1 | 1 | 1 | 1 | 1 |
| Multichannel Audio Serial Port (McASP)- I2S or PCM | – | 2-ch | 2-ch | 2-ch | 2-ch |
| Inter-Integrated Circuit (I2C) | – | 1 | 1 | 1 | 1 |
| Analog-to-digital converter (ADC) | – | 4-ch, 12-bit | 4-ch, 12-bit | 4-ch, 12-bit | 4-ch, 12-bit |
| Parallel interface (8-bit PI) | – | 1 | 1 | 1 | 1 |
| General-purpose timers | – | 4 | 4 | 4 | 4 |
| Multimedia card (MMC / SD) | – | 1 | 1 | 1 | 1 |
| SECURITY FEATURES | |||||
| Wi-Fi level of security | WEP, WPS, WPA / WPA2 PSK WPA2 (802.1x), WPA3 personal and enterprise | WEP, WPS, WPA / WPA2 PSK WPA2 (802.1x), WPA3 personal and enterprise | WEP, WPS, WPA / WPA2 PSK WPA2 (802.1x), WPA3 personal and enterprise | WEP, WPS, WPA / WPA2 PSK WPA2 (802.1x), WPA3 personal and enterprise | WEP, WPS, WPA / WPA2 PSK WPA2 (802.1x), WPA3 personal and enterprise |
| Secure sockets (SSL v3 or TLS 1.0 /1.1/ 1.2) | 6 | 6 | 6 | 6 | 6 |
| Additional networking security | Unique Device Identity Trusted Root-Certificate Catalog TI Root-of-Trust Public key |
Unique Device Identity Trusted Root-Certificate Catalog TI Root-of-Trust Public key |
Unique Device Identity Trusted Root-Certificate Catalog TI Root-of-Trust Public key |
Unique Device Identity Trusted Root-Certificate Catalog TI Root-of-Trust Public key |
Unique Device Identity Trusted Root-Certificate Catalog TI Root-of-Trust Public key |
| Hardware acceleration | Hardware Crypto Engines | Hardware Crypto Engines | Hardware Crypto Engines | Hardware Crypto Engines | Hardware Crypto Engines |
| Secure boot | – | Yes | Yes | Yes | Yes |
| Enhanced Application Level Security | – | File system security Secure key storage Software tamper detection Cloning protection Initial secure programming |
File system security Secure key storage Software tamper detection Cloning protection Initial secure programming |
File system security Secure key storage Software tamper detection Cloning protection Initial secure programming |
File system security Secure key storage Software tamper detection Cloning protection Initial secure programming |
6.1 Related Products
For information about other devices in this family of products or related products see the links below.
- The SimpleLink™ MCU Portfoliooffers a single development environment that delivers flexible hardware, software and tool options for customers developing wired and wireless applications. With 100 percent code reuse across host MCUs, Wi-Fi®, Bluetooth® low energy, Sub-1GHz devices and more, choose the MCU or connectivity standard that fits your design. A one-time investment with the SimpleLink software development kit (SDK) allows you to reuse often, opening the door to create unlimited applications.
- Companion ProductsReview products that are frequently purchased or used in conjunction with this product.
- SimpleLink™ Wi-Fi® FamilyThe SimpleLink Wi-Fi Family offers several Internet-on-a chip solutions, which address the need of battery operated, security enabled products. Texas instruments offers a single chip wireless microcontroller and a wireless network processor which can be paired with any MCU, to allow developers to design new wi-fi products, or upgrade existing products with wi-fi capabilities.
- BoosterPack™ Plug-In ModulesBoosterPack™ Plug-In Modules extend the functionality of TI LaunchPad Kit. Application specific BoosterPack Plug in modules allow you to explore a broad range of applications, including capacitive touch, wireless sensing, LED Lighting control, and more. Stack multiple BoosterPack modules onto a single LaunchPad kit to further enhance the functionality of your design.
- Reference Designs for CC3200 and CC3220 ModulesTI Designs Reference Design Library is a robust reference design library spanning analog, embedded processor and connectivity. Created by TI experts to help you jump start your system design, all TI Designs include schematic or block diagrams, BOMs and design files to speed your time to market. Search and download designs at ti.com/tidesigns.
- SimpleLink™ Wi-Fi® CC3220 SDKThe SimpleLink Wi-Fi CC3220 SDK contains drivers for the CC3220 programmable MCU, sample applications, and documentation required to start development with CC3220 solutions.
7 Terminal Configuration and Functions
7.1 CC3220MODx and CC3220MODAx Pin Diagram
Figure 7-1 shows the pin diagram for the CC3220MODx module.
Figure 7-1 shows the approximate location of pins on the module. For the actual mechanical diagram, see Section 13.
Figure 7-1 CC3220MODx Pin Diagram Bottom ViewFigure 7-2 shows the pin diagram for the CC3220MODAx module.
Figure 7-2 CC3220MODAx Pin Diagram Bottom View7.2 Pin Attributes
Section 7.2.1 lists the pin descriptions of the CC3220MODx and CC3220MODAx module.
7.2.1 Module Pin Attributes
| MODULE PIN | TYPE(1) | CC3220 DEVICE PIN NO. | MODULE PIN DESCRIPTION | |
|---|---|---|---|---|
| NO. | NAME | |||
| 1 | GND | – | – | Ground |
| 2 | GND | – | – | Ground |
| 3 | GPIO10 | I/O | 1 | GPIO(2) |
| 4 | GPIO11 | I/O | 2 | GPIO(2) |
| 5 | GPIO14 | I/O | 5 | GPIO(2) |
| 6 | GPIO15 | I/O | 6 | GPIO(2) |
| 7 | GPIO16 | I/O | 7 | GPIO(2) |
| 8 | GPIO17 | I/O | 8 | GPIO(2) |
| 9 | GPIO12 | I/O | 3 | GPIO(2) |
| 10 | GPIO13 | I/O | 4 | GPIO(2) |
| 11 | GPIO22 | I/O | 15 | GPIO(2) |
| 12 | JTAG_TDI | I/O | 16 | JTAG TDI input. Leave unconnected if not used on product(2) |
| 13 | FLASH_SPI_MISO | I | – | External Serial Flash Programming: SPI data in |
| 14 | FLASH_SPI_nCS_IN | I | – | External Serial Flash Programming: SPI chip select (active low) |
| 15 | FLASH_SPI_CLK | I | – | External Serial Flash Programming: SPI clock |
| 16 | GND | – | – | Ground |
| 17 | FLASH_SPI_MOSI | O | – | External Serial Flash Programming: SPI data out |
| 18 | JTAG_TDO | I/O | 17 | JTAG TDO output. Leave unconnected if not used on product(1) |
| 19 | GPIO28 | I/O | 18 | GPIO(2) |
| 21 | JTAG_TCK | I/O | 19 | JTAG TCK input. Leave unconnected if not used on product.(2) |
| 22 | JTAG_TMS | I/O | 20 | JTAG TMS input. Leave unconnected if not used on product.(2) |
| 23 | SOP2 | – | 21 | See Section 9.9.1 for SOP[2:0] configuration modes. |
| 24 | SOP1 | – | 34 | See Section 9.9.1 for SOP[2:0] configuration modes. |
| 25 | ANT_SEL1 | I/O | 29 | Antenna selection control(2) |
| 26 | ANT_SEL2 | I/O | 30 | Antenna selection control(2) |
| 27 | GND | – | – | Ground |
| 28 | GND | – | – | Ground |
| 30 | GND | – | – | Ground |
| 31 | RF_BG | I/O | 31 | 2.4-GHz RF input/output |
| 32 | GND | – | – | Ground |
| 34 | SOP0 | – | 35 | See Section 9.9.1 for SOP[2:0] configuration modes. |
| 35 | nRESET | I | 32 | There is an internal,
100 kΩ, pull-up resistor option from the nRESET pin to VBAT_RESET.
Note: VBAT_RESET is not connected to VBAT1 or VBAT2 within the
module. The following connection schemes are recommended:
|
| 36 | VBAT_RESET | – | 37 | |
| 37 | VBAT1 | Power | 39 | Power supply for the module, must be connected to battery (2.3 V to 3.6 V) |
| 38 | GND | – | – | Ground |
| 40 | VBAT2 | Power | 10, 44, 54 | Power supply for the module, must be connected to battery (2.3 V to 3.6 V) |
| 42 | GPIO30 | I/O | 53 | GPIO(2) |
| 43 | GND | – | – | Ground |
| 44 | GPIO0 | I/O | 50 | GPIO(2) |
| 46 | GPIO1 | I/O | 55 | GPIO(2) |
| 47 | GPIO2 | I/O | 57 | GPIO(2) |
| 48 | GPIO3 | I/O | 58 | GPIO(2) |
| 49 | GPIO4 | I/O | 59 | GPIO(2) |
| 50 | GPIO5 | I/O | 60 | GPIO(2) |
| 51 | GPIO6 | I/O | 61 | GPIO(2) |
| 52 | GPIO7 | I/O | 62 | GPIO(2) |
| 53 | GPIO8 | I/O | 63 | GPIO(2) |
| 54 | GPIO9 | I/O | 64 | GPIO(2) |
| 55 | GND | – | – | Thermal ground |
| 56 | GND | – | – | Thermal ground |
| 57 | GND | – | – | Thermal ground |
| 58 | GND | – | – | Thermal ground |
| 59 | GND | – | – | Thermal ground |
| 60 | GND | – | – | Thermal ground |
| 61 | GND | – | – | Thermal ground |
| 62 | GND | – | – | Thermal ground |
| 63 | GND | – | – | Thermal ground |
(1) I = input; O = output; I/O = bidirectional
(2) For pin multiplexing details, see Table 7-3.
7.3 Connections for Unused Pins
All unused pins must be left as no connect (NC) pins. Table 7-1 and Table 7-2 list the NC pins on the CC3220MODx and CC3220MODAx modules, respectively.
Table 7-1 Connections for Unused
Pins
| PIN | DEFAULT FUNCTION | STATE AT RESET AND HIBERNATE | I/O TYPE | DESCRIPTION |
|---|---|---|---|---|
| 20 | NC | WLAN analog | – | Reserved. Do not connect. |
| 29 | NC | WLAN analog | – | Reserved. Do not connect. |
| 33 | NC | WLAN analog | – | Reserved. Do not connect. |
| 39 | NC | WLAN analog | – | Reserved. Do not connect. |
| 41 | NC | WLAN analog | – | Reserved. Do not connect. |
| 45 | NC | WLAN analog | – | Reserved. Do not connect. |
Table 7-2 CC3220MODAx Connections for
Unused Pins
| PIN | DEFAULT FUNCTION | STATE AT RESET AND HIBERNATE | I/O TYPE | DESCRIPTION |
|---|---|---|---|---|
| 20 | NC | WLAN analog | – | Reserved. Do not connect. |
| 29 | NC | WLAN analog | – | Reserved. Do not connect. |
| 31 | NC | WLAN analog | – | Reserved. Do not connect. |
| 33 | NC | WLAN analog | – | Reserved. Do not connect. |
| 39 | NC | WLAN analog | – | Reserved. Do not connect. |
| 41 | NC | WLAN analog | – | Reserved. Do not connect. |
| 45 | NC | WLAN analog | – | Reserved. Do not connect. |
7.4 Pin Attributes and Pin Multiplexing
The module makes extensive use of pin multiplexing to accommodate the large number of peripheral functions in the smallest possible package. To achieve this configuration, pin multiplexing is controlled using a combination of hardware configuration (at module reset) and register control.
The board and software designers are responsible for the proper pin multiplexing configuration. Hardware does not ensure that the proper pin multiplexing options are selected for the peripherals or interface mode used. Table 7-3 describes the general pin attributes and presents an overview of pin multiplexing. All pin multiplexing options are configurable using the pin MUX registers. The following special considerations apply:
- All I/Os support drive strengths of 2, 4, and 6 mA. Drive strength is individually configurable for each pin.
- All I/Os support 10-μA pullup and pulldown resistors.
- By default, all I/Os float in the Hibernate state. However, the default state can be changed by SW.
- All digital I/Os are non fail-safe.
Note:
If an external device drives a positive voltage to the signal pads and the CC3220MODx or CC3220MODAx modules are not powered, DC is drawn from the other device. If the drive strength of the external device is adequate, an unintentional wakeup and boot of the CC3220MODx or CC3220MODAx modules can occur. To prevent current draw, TI recommends any one of the following conditions:
- All devices interfaced to CC3220MODx and CC3220MODAx modules must be powered from the same power rail as the chip.
- Use level shifters between the device and any external devices fed from other independent rails.
- The nRESET pin of the CC3220MODx and CC3220MODAx modules must be held low until the VBAT supply to the module is driven and stable.
- All GPIO pins default to high impedance unless programmed by the MCU. The bootloader sets the TDI, TDO, TCK, TMS, and Flash_SPI pins to mode 1. All the other pins are left in the Hi-Z state.
Table 7-3 Pin Attributes and Pin
Multiplexing
| GENERAL PIN ATTRIBUTES | FUNCTION | PAD STATES | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Pkg. Pin | Pin Alias | Use | Select as Wakeup Source | Config. Addl. Analog Mux | Muxed With JTAG | Dig. Pin Mux Config. Reg. | Dig. Pin Mux Config. Mode Value | Signal Name | Signal Description | Signal Direction | LPDS(1) | Hib(2) | nRESET = 0 |
| 1 | GND | GND | N/A | N/A | N/A | N/A | N/A | GND | GND | N/A | N/A | N/A | N/A |
| 2 | GND | GND | N/A | N/A | N/A | N/A | N/A | GND | GND | N/A | N/A | N/A | N/A |
| 3 | GPIO10 | I/O | No | No | No | GPIO_PAD_ CONFIG_10 (0x4402 E0C8) |
0 | GPIO10 | GPIO | I/O | Hi-Z, Pull, Drive |
Hi-Z, Pull, Drive |
Hi-Z |
| 1 | I2C_SCL | I2C clock | I/O (open drain) |
Hi-Z, Pull, Drive |
|||||||||
| 3 | GT_PWM06 | Pulse-width modulated O/P | O | Hi-Z, Pull, Drive |
|||||||||
| 7 | UART1_TX | UART TX data | O | 1 | |||||||||
| 6 | SDCARD_CLK | SD card clock | O | 0 | |||||||||
| 12 | GT_CCP01 | Timer capture port | I | Hi-Z, Pull, Drive |
|||||||||
| 4 | GPIO11 | I/O | Yes | No | No | GPIO_PAD_ CONFIG_11 (0x4402 E0CC) |
0 | GPIO11 | GPIO | I/O | Hi-Z, Pull, Drive |
Hi-Z, Pull, Drive |
Hi-Z |
| 1 | I2C_SDA | I2C data | I/O (open drain) |
Hi-Z, Pull, Drive |
|||||||||
| 3 | GT_PWM07 | Pulse-width modulated O/P | O | Hi-Z, Pull, Drive |
|||||||||
| 4 | pXCLK (XVCLK) | Free clock to parallel camera | O | 0 | |||||||||
| 6 | SDCARD_CMD | SD card command line | I/O (open drain) |
Hi-Z, Pull, Drive |
|||||||||
| 7 | UART1_RX | UART RX data | I | Hi-Z, Pull, Drive |
|||||||||
| 12 | GT_CCP02 | Timer capture port | I | Hi-Z, Pull, Drive |
|||||||||
| 13 | MCAFSX | I2S audio port frame sync | O | Hi-Z, Pull, Drive |
|||||||||
| 5 | GPIO14 | I/O | No | No | No | GPIO_PAD_ CONFIG_14 (0x4402 E0D8) |
0 | GPIO14 | GPIO | I/O | Hi-Z, Pull, Drive |
Hi-Z, Pull, Drive |
Hi-Z |
| 5 | I2C_SCL | I2C clock | I/O (open drain) |
||||||||||
| 7 | GSPI_CLK | General SPI clock | I/O | ||||||||||
| 4 | pDATA8 (CAM_D4) | Parallel camera data bit 4 | I | ||||||||||
| 12 | GT_CCP05 | Timer capture port | I | ||||||||||
| 6 | GPIO15 | I/O | No | No | No | GPIO_PAD_ CONFIG_15 (0x4402 E0DC) |
0 | GPIO15 | GPIO | I/O | Hi-Z, Pull, Drive |
Hi-Z, Pull, Drive |
Hi-Z |
| 5 | I2C_SDA | I2C data | I/O (open drain) |
||||||||||
| 7 | GSPI_MISO | General SPI MISO | I/O | ||||||||||
| 4 | pDATA9 (CAM_D5) | Parallel camera data bit 5 | I | ||||||||||
| 13 | GT_CCP06 | Timer capture port | I | ||||||||||
| 8 | SDCARD_ DATA0 |
SD card data | I/O | ||||||||||
| 7 | GPIO16 | I/O | No | No | No | GPIO_PAD_ CONFIG_16 (0x4402 E0E0) |
0 | GPIO16 | GPIO | I/O | Hi-Z, Pull, Drive |
Hi-Z, Pull, Drive |
Hi-Z |
| Hi-Z, Pull, Drive |
|||||||||||||
| Hi-Z, Pull, Drive |
|||||||||||||
| 7 | GSPI_MOSI | General SPI MOSI | I/O | Hi-Z, Pull, Drive |
|||||||||
| 4 | pDATA10 (CAM_D6) | Parallel camera data bit 6 | I | Hi-Z, Pull, Drive |
|||||||||
| 5 | UART1_TX | UART1 TX data | O | 1 | |||||||||
| 13 | GT_CCP07 | Timer capture port | I | Hi-Z, Pull, Drive |
|||||||||
| 8 | SDCARD_CLK | SD card clock | O | Zero | |||||||||
| 8 | GPIO17 | I/O | Yes | No | No | GPIO_PAD_ CONFIG_17 (0x4402 E0E4) |
0 | GPIO17 | GPIO | I/O | Hi-Z, Pull, Drive |
Hi-Z, Pull, Drive |
Hi-Z |
| 5 | UART1_RX | UART1 RX data | I | ||||||||||
| 7 | GSPI_CS | General SPI chip select | I/O | ||||||||||
| 4 | pDATA11 (CAM_D7) | Parallel camera data bit 7 | I | ||||||||||
| 8 | SDCARD_ CMD |
SD card command line | I/O | ||||||||||
| 9 | GPIO12 | I/O | No | No | No | GPIO_PAD_ CONFIG_12 (0x4402 E0D0) |
0 | GPIO12 | GPIO | I/O | Hi-Z, Pull, Drive |
Hi-Z, Pull, Drive |
Hi-Z |
| 3 | McACLK | I2S audio port clock output | O | Hi-Z, Pull, Drive |
|||||||||
| 4 | pVS (VSYNC) | Parallel camera vertical sync | I | Hi-Z, Pull, Drive |
|||||||||
| 5 | I2C_SCL | I2C clock | I/O (open drain) |
Hi-Z, Pull, Drive |
|||||||||
| 7 | UART0_TX | UART0 TX data | O | 1 | |||||||||
| 12 | GT_CCP03 | Timer capture port | I | Hi-Z, Pull, Drive |
|||||||||
| 10 | GPIO13 | I/O | Yes | No | No | GPIO_PAD_ CONFIG_13 (0x4402 E0D4) |
0 | GPIO13 | GPIO | I/O | Hi-Z, Pull, Drive |
Hi-Z, Pull, Drive |
Hi-Z |
| 5 | I2C_SDA | I2C data | I/O (open drain) |
||||||||||
| 4 | pHS (HSYNC) | Parallel camera horizontal sync | I | ||||||||||
| 7 | UART0_RX | UART0 RX data | I | ||||||||||
| 12 | GT_CCP04 | Timer capture port | I | ||||||||||
| 11 | GPIO22 | I/O | No | No | No | GPIO_PAD_ CONFIG_22 (0x4402 E0F8) |
0 | GPIO22 | GPIO | I/O | Hi-Z, Pull, Drive |
Hi-Z, Pull, Drive |
Hi-Z |
| 7 | McAFSX | I2S audio port frame sync | O | ||||||||||
| 5 | GT_CCP04 | Timer capture port | I | ||||||||||
| 12 | JTAG_TDI | I/O | No | No | Muxed with JTAG TDI | GPIO_PAD_ CONFIG_23 (0x4402 E0FC) |
1 | TDI | JTAG TDI. Reset default pinout. | I | Hi-Z, Pull, Drive |
Hi-Z, Pull, Drive |
Hi-Z |
| 0 | GPIO23 | GPIO | I/O | ||||||||||
| 2 | UART1_TX | UART1 TX data | O | 1 | |||||||||
| 9 | I2C_SCL | I2C clock | I/O (open drain) |
Hi-Z, Pull, Drive |
|||||||||
| 13 | FLASH_ SPI_ MISO |
N/A | N/A | N/A | N/A | N/A | N/A | FLASH_SPI_MISO | Data from SPI serial Flash (fixed default) | N/A | Hi-Z | Hi-Z | Hi-Z |
| 14 | FLASH_ SPI_ nCS_IN |
N/A | N/A | N/A | N/A | N/A | N/A | FLASH_SPI_nCS_IN | Chip select to SPI serial Flash (fixed default) | N/A | 1 | Hi-Z, Pull, Drive |
Hi-Z |
| 15 | FLASH_ SPI_CLK |
N/A | N/A | N/A | N/A | N/A | N/A | FLASH_SPI_ CLK |
Clock to SPI serial Flash (fixed default) | N/A | Hi-Z, Pull, Drive(3) |
Hi-Z, Pull, Drive |
Hi-Z |
| 16 | GND | GND | N/A | N/A | N/A | N/A | N/A | GND | GND | N/A | N/A | N/A | N/A |
| 17 | FLASH_ SPI_ MOSI |
N/A | N/A | N/A | N/A | N/A | N/A | FLASH_SPI_MOSI | Data to SPI serial Flash (fixed default) | N/A | Hi-Z, Pull, Drive(3) |
Hi-Z, Pull, Drive |
Hi-Z |
| 18 | JTAG_TDO | I/O | Yes | No | Muxed with JTAG TDO | GPIO_PAD_ CONFIG_ 24 (0x4402 E100) |
1 | TDO | JTAG TDO. Reset default pinout. | O | Hi-Z, Pull, Drive |
Driven high in SWD; driven low in 4-wire JTAG | Hi-Z |
| 0 | GPIO24 | GPIO | I/O | ||||||||||
| 5 | PWM0 | Pulse-width modulated O/P | O | ||||||||||
| 2 | UART1_RX | UART1 RX data | I | ||||||||||
| 9 | I2C_SDA | I2C data | I/O (open drain) |
||||||||||
| 4 | GT_CCP06 | Timer capture port | I | ||||||||||
| 6 | McAFSX | I2S audio port frame sync | O | ||||||||||
| 19 | GPIO28 | I/O | No | No | No | GPIO_PAD_ CONFIG_ 40 (0x4402 E140) |
0 | GPIO28 | GPIO | I/O | Hi-Z, Pull, Drive |
Hi-Z, Pull, Drive |
Hi-Z |
| 20 | NC | WLAN analog | N/A | N/A | N/A | N/A | N/A | NC | Reserved | N/A | N/A | N/A | N/A |
| 21 | JTAG_TCK | I/O | No | No | Muxed
with JTAG/ SWD-TCK |
GPIO_PAD_ CONFIG_ 28 (0x4402 E110) |
1 | TCK | JTAG/SWD TCK. Reset default pinout. |
I | Hi-Z, Pull, Drive |
Hi-Z, Pull, Drive |
Hi-Z |
| 8 | GT_PWM03 | Pulse-width modulated O/P | O | ||||||||||
| 22 | JTAG_TMS | I/O | No | No | Muxed
with JTAG/ SWD-TMSC |
GPIO_PAD_ CONFIG_ 29 (0x4402 E114) |
1 | TMS | JTAG/SWD TMS. Reset default pinout. |
I/O | Hi-Z, Pull, Drive |
Hi-Z, Pull, Drive |
Hi-Z |
| 0 | GPIO29 | GPIO | |||||||||||
| 23(4) | SOP2 | O only | No | No | No | GPIO_PAD_ CONFIG_ 25 (0x4402 E104) |
0 | GPIO25 | GPIO | O | Hi-Z, Pull, Drive |
Driven Low | Hi-Z |
| 9 | GT_PWM02 | Pulse-width modulated O/P | O | Hi-Z, Pull, Drive |
|||||||||
| 2 | McAFSX | I2S audio port frame sync | O | Hi-Z, Pull, Drive |
|||||||||
| See(5) | TCXO_EN | Enable to optional external 40-MHz TCXO | O | 0 | |||||||||
| See(6) | SOP2 | Sense-on-power 2 | I | Hi-Z, Pull, Drive |
|||||||||
| 24 | SOP1 | Config sense | N/A | N/A | N/A | N/A | N/A | SOP1 | Sense-on-power 1 | N/A | N/A | N/A | N/A |
| 25(7) | ANT_SEL1 | O only | No | User config not
required (8) |
No | GPIO_PAD_ CONFIG_26 (0x4402 E108) |
0 | ANTSEL1(3) | Antenna selection control | O | Hi-Z, Pull, Drive |
Hi-Z, Pull, Drive |
Hi-Z |
| 26(7) | ANT_SEL2 | O only | No | User config not
required (8) |
No | GPIO_PAD_ CONFIG_27 (0x4402 E10C) |
0 | ANTSEL2(3) | Antenna selection control | O | Hi-Z, Pull, Drive |
Hi-Z, Pull, Drive |
Hi-Z |
| 27 | GND | GND | N/A | N/A | N/A | N/A | N/A | GND | GND | N/A | N/A | N/A | N/A |
| 28 | GND | GND | N/A | N/A | N/A | N/A | N/A | GND | GND | N/A | N/A | N/A | N/A |
| 29 | NC | WLAN analog | N/A | N/A | N/A | N/A | N/A | NC | Reserved | N/A | N/A | N/A | N/A |
| 30 | GND | GND | N/A | N/A | N/A | N/A | N/A | GND | GND | N/A | N/A | N/A | N/A |
| 31 | RF_BG | WLAN analog | N/A | N/A | N/A | N/A | N/A | CC3220MODx: RF BG band CC3220MODAx: NC |
N/A | N/A | N/A | N/A | N/A |
| 32 | GND | GND | N/A | N/A | N/A | N/A | N/A | GND | GND | N/A | N/A | N/A | N/A |
| 33 | NC | WLAN analog | N/A | N/A | N/A | N/A | NC | Reserved | |||||
| 34 | SOP0 | Config sense | N/A | N/A | N/A | N/A | N/A | SOP0 | Sense-on-power 0 | N/A | N/A | N/A | N/A |
| 35 | nRESET | Global reset | N/A | N/A | N/A | N/A | N/A | nRESET | Master chip reset. Active low. | N/A | N/A | N/A | N/A |
| 36 | VBAT_ RESET |
Global reset | N/A | N/A | N/A | N/A | N/A | VBAT_RESET | VBAT to nRESET pullup resistor | N/A | N/A | N/A | N/A |
| 37 | VBAT1 | Supply input | N/A | N/A | N/A | N/A | N/A | VBAT1 | Analog DC/DC input (connected to chip input supply [VBAT]) | N/A | N/A | N/A | N/A |
| 38 | GND | GND | N/A | N/A | N/A | N/A | N/A | GND | GND | N/A | N/A | N/A | N/A |
| 39 | NC | WLAN analog | N/A | N/A | N/A | N/A | N/A | NC | Reserved | N/A | N/A | N/A | N/A |
| 40 | VBAT2 | Supply input | N/A | N/A | N/A | N/A | N/A | VBAT2 | Analog input supply VBAT | N/A | N/A | N/A | N/A |
| 41 | NC | WLAN analog | N/A | N/A | N/A | N/A | N/A | NC | Reserved | N/A | N/A | N/A | N/A |
| 42 | GPIO30 | I/O | No | User
config not required (8) |
No | GPIO_PAD_ CONFIG_30 (0x4402 E118) |
0 | GPIO30 | GPIO | I/O | Hi-Z, Pull, Drive |
Hi-Z, Pull, Drive |
Hi-Z |
| 9 | UART0_TX | UART0 TX data | O | 1 | |||||||||
| 2 | McACLK | I2S audio port clock | O | Hi-Z, Pull, Drive |
|||||||||
| 3 | McAFSX | I2S audio port frame sync | O | Hi-Z, Pull, Drive |
|||||||||
| 4 | GT_CCP05 | Timer capture port | I | Hi-Z, Pull, Drive |
|||||||||
| 7 | GSPI_MISO | General SPI MISO | I/O | Hi-Z, Pull, Drive |
|||||||||
| 43 | GND | GND | N/A | N/A | N/A | N/A | N/A | GND | GND | N/A | N/A | N/A | N/A |
| 44 | GPIO0 | I/O | No | User
config not required (8) |
No | GPIO_PAD_ CONFIG_0 (0x4402 E0A0) |
0 | GPIO0 | GPIO | I/O | Hi-Z, Pull, Drive |
Hi-Z, Pull, Drive |
Hi-Z |
| 12 | UART0_CTS | UART0 Clear-to-Send input (active low) | I | Hi-Z, Pull, Drive |
Hi-Z, Pull, Drive |
Hi-Z | |||||||
| 6 | McAXR1 | I2S audio port data 1 (RX/TX) | I/O | Hi-Z, Pull, Drive |
|||||||||
| 7 | GT_CCP00 | Timer capture port | I | Hi-Z, Pull, Drive |
|||||||||
| 9 | GSPI_CS | General SPI chip select | I/O | Hi-Z, Pull, Drive |
|||||||||
| 10 | UART1_RTS | UART1 Request-to-Send (active low) | O | 1 | |||||||||
| 3 | UART0_RTS | UART0 Request-to-Send (active low) | O | 1 | |||||||||
| 4 | McAXR0 | I2S audio port data 0 (RX/TX) | I/O | Hi-Z, Pull, Drive |
|||||||||
| 45 | NC | WLAN analog | N/A | N/A | N/A | N/A | N/A | NC | Reserved | N/A | N/A | N/A | N/A |
| 46 | GPIO1 | I/O | No | No | No | GPIO_PAD_ CONFIG_1 (0x4402 E0A4) |
0 | GPIO1 | GPIO | I/O | Hi-Z, Pull, Drive |
Hi-Z, Pull, Drive |
Hi-Z |
| 3 | UART0_TX | UART0 TX data | O | 1 | |||||||||
| 4 | pCLK (PIXCLK) | Pixel clock from parallel camera sensor | I | Hi-Z, Pull, Drive |
|||||||||
| 6 | UART1_TX | UART1 TX data | O | 1 | |||||||||
| 7 | GT_CCP01 | Timer capture port | I | Hi-Z, Pull, Drive |
|||||||||
| 47(10) | GPIO2 | Analog input (up to 1.8 V)/ digital I/O | Yes | See(9) | No | GPIO_PAD_ CONFIG_2 (0x4402 E0A8) |
See(5) | ADC_CH0 | ADC channel 0 input (1.5-V max) | I | Hi-Z, Pull, Drive |
Hi-Z, Pull, Drive |
Hi-Z |
| 0 | GPIO2 | GPIO | I/O | Hi-Z, Pull, Drive |
|||||||||
| 3 | UART0_RX | UART0 RX data | I | Hi-Z, Pull, Drive |
|||||||||
| 6 | UART1_RX | UART1 RX data | I | Hi-Z, Pull, Drive |
|||||||||
| 7 | GT_CCP02 | Timer capture port | I | Hi-Z, Pull, Drive |
|||||||||
| 48(10) | GPIO3 | Analog input (up to 1.8 V)/ digital I/O | No | See(9) | No | GPIO_PAD_ CONFIG_3 (0x4402 E0AC) |
See(5) | ADC_CH1 | ADC channel 1 input (1.5-V max) | I | Hi-Z, Pull, Drive |
Hi-Z, Pull, Drive |
Hi-Z |
| 0 | GPIO3 | GPIO | I/O | Hi-Z, Pull, Drive |
|||||||||
| 6 | UART1_TX | UART1 TX data | O | 1 | |||||||||
| 4 | pDATA7 (CAM_D3) | Parallel camera data bit 3 | I | Hi-Z, Pull, Drive |
|||||||||
| 49(10) | GPIO4 | Analog input (up to 1.8 V)/ digital I/O | Yes | See(9) | Yes | GPIO_PAD_ CONFIG_4 (0x4402 E0B0) |
See(5) | ADC_CH2 | ADC channel 2 input (1.5-V max) | I | Hi-Z, Pull, Drive |
Hi-Z, Pull, Drive |
Hi-Z |
| 0 | GPIO4 | GPIO | I/O | Hi-Z, Pull, Drive |
|||||||||
| 6 | UART1_RX | UART1 RX data | I | Hi-Z, Pull, Drive |
|||||||||
| 4 | pDATA6 (CAM_D2) | Parallel camera data bit 2 | I | Hi-Z, Pull, Drive |
|||||||||
| 50(10) | GPIO5 | Analog input up to 1.5 V | No | See(9) | No | GPIO_PAD_ CONFIG_5 (0x4402 E0B4) |
See(5) | ADC_CH3 | ADC channel 3 input (1.5 V max) | I | i-Z, Pull, Drive |
Hi-Z, Pull, Drive |
Hi-Z |
| 0 | GPIO5 | GPIO | I/O | Hi-Z, Pull, Drive |
|||||||||
| 4 | pDATA5 (CAM_D1) | Parallel camera data bit 1 | I | Hi-Z, Pull, Drive |
|||||||||
| 6 | McAXR1 | I2S audio port data 1 (RX, TX) | I/O | Hi-Z, Pull, Drive |
|||||||||
| 7 | GT_CCP05 | Timer capture port | I | Hi-Z, Pull, Drive |
|||||||||
| 51 | GPIO6 | I/O | No | No | No | GPIO_PAD_ CONFIG_6 (0x4402 E0B8) |
0 | GPIO6 | GPIO | I/O | Hi-Z, Pull, Drive |
Hi-Z, Pull, Drive |
Hi-Z |
| 5 | UART0_RTS | UART0 Request-to-Send (active low) | O | 1 | |||||||||
| 4 | pDATA4 (CAM_D0) | Parallel camera data bit 0 | I | Hi-Z, Pull, Drive |
|||||||||
| 3 | UART1_CTS | UART1 Clear to send (active low) | I | Hi-Z, Pull, Drive |
|||||||||
| 6 | UART0_CTS | UART0 Clear to send (active low) | I | Hi-Z, Pull, Drive |
|||||||||
| 7 | GT_CCP06 | Timer capture port | I | Hi-Z, Pull, Drive |
|||||||||
| 52 | GPIO7 | I/O | No | No | No | GPIO_PAD_ CONFIG_7 (0x4402 E0BC) |
0 | GPIO7 | GPIO | I/O | Hi-Z, Pull, Drive |
Hi-Z, Pull, Drive |
Hi-Z |
| 13 | McACLK | I2S audio port clock | O | Hi-Z, Pull, Drive |
|||||||||
| 3 | UART1_RTS | UART1 Request to send (active low) | O | 1 | |||||||||
| 10 | UART0_RTS | UART0 Request to send (active low) | O | 1 | |||||||||
| 11 | UART0_TX | UART0 TX data | O | 1 | |||||||||
| 53 | GPIO8 | I/O | No | No | No | GPIO_PAD_ CONFIG_8 (0x4402 E0C0) |
0 | GPIO8 | GPIO | I/O | Hi-Z, Pull, Drive |
Hi-Z, Pull, Drive |
Hi-Z |
| 6 | SDCARD_IRQ | Interrupt from SD card (future support) | I | ||||||||||
| 7 | McAFSX | I2S audio port frame sync | O | ||||||||||
| 12 | GT_CCP06 | Timer capture port | I | ||||||||||
| 54 | GPIO9 | I/O | No | No | No | GPIO_PAD_ CONFIG_9 (0x4402 E0C4) |
0 | GPIO9 | GPIO | I/O | Hi-Z, Pull, Drive |
Hi-Z, Pull, Drive |
Hi-Z |
| 3 | GT_PWM05 | Pulse-width modulated O/P | O | ||||||||||
| 6 | SDCARD_ DATA0 |
SD card data | I/O | ||||||||||
| 7 | McAXR0 | I2S audio port data (RX, TX) | I/O | ||||||||||
| 12 | GT_CCP00 | Timer capture port | I | ||||||||||
| 55 | GND | GND | N/A | N/A | N/A | N/A | N/A | GND | GND | N/A | N/A | N/A | N/A |
| 56 | GND | GND | N/A | N/A | N/A | N/A | N/A | GND | GND | N/A | N/A | N/A | N/A |
| 57 | GND | GND | N/A | N/A | N/A | N/A | N/A | GND | GND | N/A | N/A | N/A | N/A |
| 58 | GND | GND | N/A | N/A | N/A | N/A | N/A | GND | GND | N/A | N/A | N/A | N/A |
| 59 | GND | GND | N/A | N/A | N/A | N/A | N/A | GND | GND | N/A | N/A | N/A | N/A |
| 60 | GND | GND | N/A | N/A | N/A | N/A | N/A | GND | GND | N/A | N/A | N/A | N/A |
| 61 | GND | GND | N/A | N/A | N/A | N/A | N/A | GND | GND | N/A | N/A | N/A | N/A |
| 62 | GND | GND | N/A | N/A | N/A | N/A | N/A | GND | GND | N/A | N/A | N/A | N/A |
| 63 | GND | GND | N/A | N/A | N/A | N/A | N/A | GND | GND | N/A | N/A | N/A | N/A |
(1) LPDS state: The state of unused I/Os is Hi-Z. Software may
program the I/Os to be input with pull or drive (regardless of active pin
configuration), according to the need.
(2) Hibernate mode: The state of the I/Os is Hi-Z. Software may
program the I/Os to be input with pull or drive (regardless of active pin
configuration), according to the need.
(3) To minimize leakage in some serial Flash vendors during LPDS, TI
recommends that the user application always enables internal weak pulldowns on
FLASH_SPI_DIN, FLASH_SPI_DOUT, and FLASH_SPI_CLK pins.
(4) Pin has dual functions: as a SOP[2] (device operation mode), and
as an external TCXO enable. As a TXCO enable, the pin is an output on power up
and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z
state but is pulled down for SOP mode to disable TCXO. Because of the SOP
functionality, the pin must be used as an output only.
(5) For details on proper use, see Drive Strength and Reset States for Analog-Digital Multiplexed
Pins.
(6) Pin is one of three that must have a passive pullup or pulldown
resistor onboard to configure the chip hardware power-up mode. For this reason,
the pin must be output only when used for digital functions.
(7) This pin is reserved for WLAN antenna selection, controlling an
external RF switch that multiplexes the RF pin of the CC3220MODx module between
two antennas. These pins must not be used for other functionalities.
(8) Device firmware automatically enables the digital path during
ROM boot.
(9) Requires user configuration to enable the analog switch of the
ADC channel. (Switch is off by default.) The digital I/O is always connected and
must be made Hi-Z before enabling the ADC switch.
(10) Pin is shared by the ADC inputs and digital I/O pad cells.
Note:
The ADC inputs are tolerant up to 1.8 V (see Section 8.14.5.6 for further details on the useable range of the ADC). The digital pads can tolerate up to 3.6 V. Hence, take care to prevent accidental damage to the ADC inputs. TI recommends first disabling the output buffers of the digital I/Os corresponding to the desired ADC channel (that is, converted to Hi-Z state), and thereafter disabling the respective pass switches (S7 [Pin 47], S8 [Pin 48], S9 [Pin 49], and S10 [Pin 50]). For more information, see Section 7.5.
7.5 Drive Strength and Reset States for Analog-Digital Multiplexed Pins
Table 7-4 describes the use, drive strength, and default state of analog- and digital-multiplexed pins at first-time power up and reset (nRESET pulled low).
Table 7-4 Drive Strength and Reset States for Analog-Digital Multiplexed Pins
| PIN | BOARD LEVEL CONFIGURATION AND USE | DEFAULT STATE AT FIRST POWER UP OR FORCED RESET | STATE AFTER CONFIGURATION OF ANALOG SWITCHES (ACTIVE, LPDS, and HIB POWER MODES) | MAXIMUM EFFECTIVE DRIVE STRENGTH (mA) |
|---|---|---|---|---|
| 25 | Connected to the enable pin of the RF switch (ANT_SEL1). Other use is not recommended. | Analog is isolated. The digital I/O cell is also isolated. | Determined by the I/O state, as are other digital I/Os. | 4 |
| 26 | Connected to the enable pin of the RF switch (ANT_SEL2). Other use is not recommended. | Analog is isolated. The digital I/O cell is also isolated. | Determined by the I/O state, as are other digital I/Os. | 4 |
| 44 | Generic I/O | Analog is isolated. The digital I/O cell is also isolated. | Determined by the I/O state, as are other digital I/Os. | 4 |
| 42 | Generic I/O | Analog is isolated. The digital I/O cell is also isolated. | Determined by the I/O state, as are other digital I/Os. | 4 |
| 47 | Analog signal (1.8-V absolute, 1.46-V full scale) | ADC is isolated. The digital I/O cell is also isolated. | Determined by the I/O state, as are other digital I/Os. | 4 |
| 48 | Analog signal (1.8-V absolute, 1.46-V full scale) | ADC is isolated. The digital I/O cell is also isolated. | Determined by the I/O state, as are other digital I/Os. | 4 |
| 49 | Analog signal (1.8-V absolute, 1.46-V full scale) | ADC is isolated. The digital I/O cell is also isolated. | Determined by the I/O state, as are other digital I/Os. | 4 |
| 50 | Analog signal (1.8-V absolute, 1.46-V full scale) | ADC is isolated. The digital I/O cell is also isolated. | Determined by the I/O state, as are other digital I/Os. | 4 |
