ZHCSFV6E august   2016  – november 2020 DS90UB933-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1.     Pin Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Recommended Serializer Timing For PCLK
    7. 6.7  AC Timing Specifications (SCL, SDA) - I2C-Compatible
    8. 6.8  Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C-Compatible
    9. 6.9  Serializer Switching Characteristics
    10. 6.10 Timing Diagrams
    11. 6.11 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial Frame Format
      2. 7.3.2 Line Rate Calculations for the DS90UB933/934
      3. 7.3.3 Error Detection
      4. 7.3.4 Synchronizing Multiple Cameras
      5. 7.3.5 General Purpose I/O (GPIO) Descriptions
      6. 7.3.6 LVCMOS V(VDDIO) Option
      7. 7.3.7 Pixel Clock Edge Select (TRFB / RRFB)
      8. 7.3.8 Power Down
    4. 7.4 Device Functional Modes
      1. 7.4.1 DS90UB933/934 Operation With External Oscillator as Reference Clock
      2. 7.4.2 DS90UB933/934 Operation With Pixel Clock From Imager as Reference Clock
      3. 7.4.3 MODE Pin on Serializer
      4. 7.4.4 Internal Oscillator
      5. 7.4.5 Built-In Self Test
      6. 7.4.6 BIST Configuration and Status
      7. 7.4.7 Sample BIST Sequence
    5. 7.5 Programming
      1. 7.5.1 Programmable Controller
      2. 7.5.2 Description of Bidirectional Control Bus and I2C Modes
      3. 7.5.3 I2C Pass-Through
      4. 7.5.4 Slave Clock Stretching
      5. 7.5.5 IDX Address Decoder on the Serializer
      6. 7.5.6 Multiple Device Addressing
    6. 7.6 Register Maps
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Over Coax
      2. 8.1.2 Power-Up Requirements and PDB Pin
      3. 8.1.3 AC Coupling
      4. 8.1.4 Transmission Media
    2. 8.2 Typical Applications
      1. 8.2.1 Coax Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 STP Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 62
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Interconnect Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表

6.5 Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
LVCMOS DC SPECIFICATIONS 3.3 V I/O (SER INPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIHHigh level input voltageVIN = 3 V to 3.6 V2VINV
VILLow level input voltageVIN = 3 V to 3.6 VGND0.8V
IINInput currentVIN = 0 V or 3.6 V, VIN = 3 V to 3.6 V–20±120µA
VOHHigh level output voltageV(VDDIO) = 3 V to 3.6 V, IOH = −4 mA2.4V(VDDIO)V
VOLLow level output voltageV(VDDIO) = 3 V to 3.6 V, IOL = 4 mAGND0.4V
IOSOutput short-circuit currentVOUT = 0 VSerializer
GPO outputs		–15mA
IOZTri-state output currentPDB = 0 V,
VOUT = 0 V or V(VDDIO)		Serializer
GPO outputs		–2020µA
CGPOPin capacitanceGPO [3:0]1.5pF
LVCMOS DC SPECIFICATIONS 1.8 V I/O (SER INPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIHHigh level input voltageVIN = 1.71 V to 1.89 V0.65 VINVINV
VILLow level input voltageVIN = 1.71 V to 1.89 VGND0.35 VIN
IINInput currentVIN = 0 V or 1.89 V, VIN = 1.71 V to 1.89 V–20±120µA
VOHHigh level output voltageV(VDDIO) = 1.71 V to 1.89 V, IOH = −4 mAV(VDDIO) – 0.45V(VDDIO)V
VOLLow level output voltageV(VDDIO) = 1.71 V to 1.89 V IOL = 4 mAGND0.45V
IOSOutput short-circuit currentVOUT = 0 VSerializer
GPO outputs		–11mA
IOZTri-state output currentPDB = 0 V,
VOUT = 0 V or V(VDDIO)		Serializer
GPO outputs		–2020µA
CGPOPin capacitanceGPO [3:0]1.5pF
IIN_STRAPStrap pin input currentVIN = 0 V to VDD_nMODE, IDX–11µA
LVCMOS DC SPECIFICATIONS 2.8 V I/O (SER INPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIHHigh level input voltageVIN = 2.52 V to 3.08 V0.7 VINVINV
VILLow level input voltageVIN = 2.52 V to 3.08 VGND0.3 VIN
IINInput currentVIN = 0 V or 3.08 V, VIN = 2.52 V to 3.08 V–20±120µA
VOHHigh level output voltageV(VDDIO) = 2.52 V to 3.08 V, IOH = −4 mAV(VDDIO) - 0.4V(VDDIO)V
VOLLow level output voltageV(VDDIO) =2.52 V to 3.08V IOL = 4 mAGND0.4V
IOSOutput short-circuit currentVOUT = 0 VSerializer
GPO outputs		–11mA
IOZTri-state output currentPDB = 0 V,
VOUT = 0 V or V(VDDIO)		Serializer
GPO outputs		–2020µA
CGPOPin capacitanceGPO [3:0]1.5pF
CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT–)
VODDifferential output voltageRL = 100 Ω (Figure 6-6)640824mV
VOUTSingle-ended output voltageRL = 50 Ω (Figure 6-6)320412
ΔVODDifferential output
voltage unbalance		RL = 100 Ω150mV
VOSOutput offset voltageRL = 100 Ω (Figure 6-6)V(VDD_n) – (VOD /2)V
ΔVOSOffset voltage unbalanceRL = 100 Ω150mV
IOSOutput short-circuit currentDOUT+ = 0 V or DOUT– = 0 V–26mA
RTDifferential internal termination resistanceDifferential across DOUT+ and DOUT–80100120Ω
Single-ended
termination resistance		DOUT+ or DOUT–405060
VID-BCBack channel differential input voltageBack Channel Frequency = 5.5 MHz(4)260mV
VIN-BCBack channel single-ended input voltage130mV
SERIALIZER SUPPLY CURRENT
IDDTSerializer (Tx)
V(VDD_n) supply current (includes load current)		RL = 100 Ω
WORST CASE pattern
(Figure 6-2)		V(VDD_n) = 1.89 V V(VDDIO) = 3.6 V
ƒ = 100 MHz, 12-bit mode
Default registers		7695mA
V(VDD_n) = 1.89 V V(VDDIO) = 3.6 V
ƒ = 75 MHz, 12-bit mode
Default registers		6180mA
IDDTSerializer (Tx)
V(VDD_n) supply current (includes load current)		RL = 100 Ω
RANDOM PRBS-7 pattern		V(VDD_n) = 1.89 V V(VDDIO) = 3.6 V
ƒ = 100 MHz, 12-bit mode
Default Registers		80mA
V(VDD_n) = 1.89 V V(VDDIO) = 3.6 V
ƒ = 75 MHz, 12-bit mode
Default Registers		64
I(VDDIO)TSerializer (Tx)
V(VDDIO) supply current (includes load current)		RL = 100 Ω
WORST CASE pattern
(Figure 6-2)		V(VDDIO) = 1.89 V
ƒ = 75 MHz, 12-bit mode
Default Registers		1.53mA
V(VDDIO) = 3.6 V
ƒ = 75 MHz, 12-bit mode
Default registers		58
IDDTZSerializer (Tx) supply current power downPDB = 0 V; All other LVCMOS inputs = 0 VV(VDDIO)=1.89 V
Default registers		3001000µA
V(VDDIO) = 3.6 V
Default registers		3001000µA
I(VDDIO)TZSerializer (Tx) V(VDDIO) supply current power downPDB = 0 V; All other LVCMOS inputs = 0 VV(VDDIO) = 1.89 V
Default registers		15100µA
V(VDDIO) = 3.6 V
Default registers		15100µA
(1) The Electrical Characteristics tables list verified specifications under the listed Section 6.3 except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not verified.
(2) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD and ΔVOD which are differential voltages.
(3) Typical values represent most likely parametric norms at 1.8 V or 3.3 V, TA = 25°C, and at the Section 6.3 at the time of product characterization and are not verified.
(4) The back channel frequency (MHz) listed is the frequency of the internal clock used to generate the encoded back channel data stream. The data rate (Mbps) of the encoded back channel stream is the back channel frequency divided by 2.