ZHCSFK1D July   2016  – January 2025 TLV700XX-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Internal Current Limit
      2. 6.3.2 Shutdown
      3. 6.3.3 Dropout Voltage
      4. 6.3.4 Undervoltage Lockout (UVLO)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Operation with VIN Less Than 2V
      2. 6.4.2 Operation with VIN Greater Than 2V
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Input and Output Capacitor Requirements
      2. 7.1.2 Transient Response
      3. 7.1.3 Thermal Protection
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input Capacitance
        2. 7.2.2.2 Output Capacitance
        3. 7.2.2.3 Thermal Calculation
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Board Layout Recommendations to Improve PSRR and Noise Performance
      3. 7.4.3 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 接收文档更新通知
    4. 8.4 支持资源
    5. 8.5 Trademarks
    6. 8.6 静电放电警告
    7. 8.7 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.2.2.1 Input Capacitance

Although not required for stability, connecting a 0.1µF to 1µF low-ESR capacitor across the IN pin and GND pin the regulator is good analog design practice.