TIDT319 December   2022

 

  1.   Description
  2.   Features
  3.   Applications
  4. 1Test Prerequisites
    1. 1.1 Voltage and Current Requirements
    2. 1.2 Considerations
    3. 1.3 Dimensions
  5. 2Testing and Results
    1. 2.1 Efficiency Graph
    2. 2.2 Loss Graph
    3. 2.3 Load Regulation
    4. 2.4 Thermal Images
      1. 2.4.1 Summary, Hottest Spot High-Side FET Q6, NVMFS5C645NL
      2. 2.4.2 Thermal Images
      3. 2.4.3 Thermal Mechanics
    5. 2.5 Bode Plots
      1. 2.5.1 Bode Plot Summary, Loop Bandwidth 16 kHz
      2. 2.5.2 24-V Input Voltage
      3. 2.5.3 36-V Input Voltage
      4. 2.5.4 48-V Input Voltage
  6. 3Waveforms for 2 × LM5143A-Q1 in Four Phase Configuration and Interleaved Operation
    1. 3.1 Switching
      1. 3.1.1 Overview of the Four Switching Phases
        1. 3.1.1.1 24-V Input Voltage
        2. 3.1.1.2 36-V Input Voltage
        3. 3.1.1.3 48-V Input Voltage
      2. 3.1.2 Low-Side FET
        1. 3.1.2.1 Switch Node to GND
        2. 3.1.2.2 Low-Side FET Gate to GND
      3. 3.1.3 High-Side FET
        1. 3.1.3.1 Switch Node to VIN
        2. 3.1.3.2 High-Side FET Gate to Switch Node
    2. 3.2 Output Voltage Ripple
    3. 3.3 Input Voltage Ripple
      1. 3.3.1 Board Input
        1. 3.3.1.1 24-V Input Voltage
        2. 3.3.1.2 36-V Input Voltage
        3. 3.3.1.3 48-V Input Voltage
      2. 3.3.2 Power Stage Input, No Input Filter
        1. 3.3.2.1 24-V Input Voltage
        2. 3.3.2.2 36-V Input Voltage
        3. 3.3.2.3 48-V Input Voltage
    4. 3.4 Load Transients
      1. 3.4.1 Load Transient 10 A to 50 A (80 %)
      2. 3.4.2 Load Transient 5 A to 50 A (90 %)
    5. 3.5 Start-Up Sequence
    6. 3.6 Shutdown Sequence
  7.   A Individual Adjusting of the Rising Edge and Falling Edge With LM5143A
    1.     A.1 2.21-Ω High and 4.75-Ω Low Resistor in Before Gate of the High-Side FET
    2.     A.2 2 × 4.75-Ω Resistors in Before Gate of the High-Side FET
  8.   B Measurements Across the Low-Side FETs to Check at All Four Phases
    1.     B.1 FET Q3
    2.     B.2 FET Q4
    3.     B.3 FET Q7
    4.     B.4 FET Q8
  9.   C ON Demand – Assembly of Thermal Interface
    1.     C.1 Thermal Interface Example

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 

Copyright © 2022, Texas Instruments Incorporated