TIDT316 December   2022

 

  1.   Description
  2.   Features
  3.   Applications
  4. 1Test Prerequisites
    1. 1.1 Voltage and Current Requirements
    2. 1.2 Considerations
    3. 1.3 Dimensions
  5. 2Testing and Results
    1. 2.1 Efficiency Graph
    2. 2.2 Loss Graph
    3. 2.3 Load Regulation
    4. 2.4 Line Regulation
    5. 2.5 Thermal Images
      1. 2.5.1 8-V Input Voltage
      2. 2.5.2 12-V Input Voltage
      3. 2.5.3 18-V Input Voltage
      4. 2.5.4 Conclusion
    6. 2.6 Bode Plots
      1. 2.6.1 5.2-V Input Voltage (Board Input, 5.0 V at Power Stage)
      2. 2.6.2 12-V Input Voltage
      3. 2.6.3 18-V Input Voltage
  6. 3Waveforms
    1. 3.1 Switching
      1. 3.1.1 Switchnode (SW) to GND
        1. 3.1.1.1 8-V Input Voltage
        2. 3.1.1.2 12-V Input Voltage
        3. 3.1.1.3 18-V Input Voltage
      2. 3.1.2 Diode D1 (Referenced to VOUT)
        1. 3.1.2.1 8-V Input Voltage
        2. 3.1.2.2 12-V Input Voltage
        3. 3.1.2.3 18-V Input Voltage
    2. 3.2 Output Voltage Ripple
    3. 3.3 Input Voltage Ripple (AC-Coupled)
      1. 3.3.1 Board Input
      2. 3.3.2 Power Stage Input
    4. 3.4 Load Transients
      1. 3.4.1 8-V Input Voltage
      2. 3.4.2 12-V Input Voltage
      3. 3.4.3 18-V Input Voltage
    5. 3.5 Start-Up Sequence
      1. 3.5.1 8-V Input Voltage
      2. 3.5.2 12-V Input Voltage
      3. 3.5.3 18-V Input Voltage
    6. 3.6 Shutdown Sequence
      1. 3.6.1 8-V Input Voltage
      2. 3.6.2 12-V Input Voltage
      3. 3.6.3 18-V Input Voltage
  7.   A Output Ripple Reduction, Output Current Capability, and Dithering Option
    1.     A.1 Output Ripple Reduction by Adding Ceramic Output Capacitors (MLCCs)
      1.      A.1.1 Initial Design
      2.      A.1.2 Adding one 47-µF X7R Ceramic Capacitor, MLCC, 10 V, X7R, 1210
      3.      A.1.3 Adding a Second 47-µF Capacitor (Final Design)
    2.     A.2 Maximum Output Current Capability at Ultra-Low Cold Cranking Using LM5157
    3.     A.3 Dithering Option via Resistor R10
      1.      A.3.1 Enabled
      2.      A.3.2 Disabled

A.2 Maximum Output Current Capability at Ultra-Low Cold Cranking Using LM5157

With assembled ORing diodes (D2, D3) at bias input and disabled UVLO (R5 = OPEN), the circuit starts to switch at input voltage higher than 3 V.

Table 4-1 shows the achievable output current at low-input voltages. Figure 4-4 represents the result from the table graphically for the input voltage at the power stage.

Table 4-1 Maximum Output Current at Low Input Voltages
Input Voltage at Power Stage Board Input Voltage Maximum Output Current
1.5 V 1.6 V 500 mA
2.0 V 2.1 V 700 mA
2.5 V 2.7 V 900 mA
3.0 V 3.2 V 1.3 A
3.5 V 3.7 V 1.6 A
4.0 V 4.2 V 1.9 A
4.5 V 4.6 V 2.1 A
5.0 V 5.1 V 2.3 A

A peak load capability of 2 A is achieved at input voltages higher than 4.5 V.

GUID-20221118-SS0I-5XMR-RPQL-ZKPPDHHSJMHG-low.jpg Figure 4-4 Maximum Output Current vs Power Stage Input Voltage