The PMP22650 reference design is a 6.6-kW, bidirectional, onboard charger. The design employs a two-phase totem pole PFC and a full-bridge CLLLC converter with synchronous rectification. The CLLLC utilizes both frequency and phase modulation to regulate the output across the required regulation range. The design uses a single processing core inside a TMS320F28388D microcontroller to control both the PFC and CLLLC. Synchronous rectification is implemented via the same microcontroller with Rogowski coil current sensors. High density is achieved through the use of high-speed GaN switches (LMG3522). The PFC is operating at 120 kHz and the CLLLC runs with a variable frequency from 200 kHz to 800 kHz. A peak system efficiency of 96.5% was achieved with an open-frame power density of 3.8 kW/L.

While the design calculations were done for a 6.6-kW output power, the design represents a suitable starting point for a 7.x-kW (for example, 7.2-kW to 7.4-kW) rated OBC operating from a 240-V input with a 32-A breaker.

Figure 1-1 OBC Front View

Figure 1-2 OBC Back View

Figure 1-3 Simplified Schematic

• 240 V_AC, 7 kW AC source
• 250 V to 450 V, 6.6 kW DC load
• 12 V, 2 A bias supply
• Refrigerated recirculating chiller

Total volume: 105.8 in³

• Red region
  • All top-side components except output bulk capacitors
  • 113 mm × 241 mm × 50 mm
• Blue region
  • Output bulk capacitors
  • 113 mm × 30 mm × 52 mm
• Green region
  • PCB and bottom-side components
  • 113 mm x 271 mm x 6.4 mm

Figure 2-1 Solution Dimensions

The power density achieved in this design is 3.8 kW/L (62.5 W/in³). The total system efficiency is 96.5%. The PFC has an efficiency of 98.5% and the CLLLC is 98%.

Efficiency data is provided in the following graphs with and without 12-V bias power. The bias supplies power to control, isolators, and gate drive. The graph in Figure 3-1 was taken under the following conditions:

• V_IN,RMS = 240 V
• V_OUT = 400 V
• Coolant Temperature: 20°C

Figure 3-1 PFC Efficiency

The graph in Figure 3-2 was taken under the following conditions:

• V_IN = 400 V
• V_OUT = 350 V
• Coolant Temperature: 20°C

Figure 3-2 CLLLC Efficiency

The graph in Figure 3-3 was taken under the following conditions:

• V_IN,RMS = 240 V
• V_OUT = 350 V
• Coolant Temperature: 20 °C

Figure 3-3 System Efficiency

The following figures summarize the total system efficiency, system losses, total harmonic distortion (THD), and the normalized output voltage regulation accuracy.

The power density achieved in this design is 3.8 kW/L (62.5 W/in³). This comes with a total system efficiency of 96.5%. Loads above 1.5 kW have a THD < 5% and the regulation accuracy of the output voltage is roughly within ±0.06%.

The graphs in Figure 3-4 use the following conditions:

• V_IN,RMS = 240 V
• V_OUT = 350 V
• Coolant Temperature: 20 °C

Figure 3-4 System Performance

The following bode plots were acquired using the onboard software frequency response analyzer inside the TMS320F28388D microcontroller. The load used in the tests was configured as a constant current sink. The microcontroller is configured to regulate a constant output voltage. The bandwidth is roughly from 1 kHz to 2.5 kHz with a phase margin in excess of 45°.

Figure 3-5 Voltage Loop Bode Plot

The following bode plots were acquired using the onboard software frequency response analyzer inside the TMS320F28388D microcontroller. The load used in the tests was configured as a constant voltage. The microcontroller is configured to regulate a constant output current. The bandwidth is roughly from 1 kHz to 2.5 kHz with a phase margin in excess of 60°.

Figure 3-6 Voltage Loop Bode Plot (Constant Voltage Load)

The following table shows efficiency and regulation data.