SWRZ166A November   2024  – June 2025 AWR2944P

 

  1.   1
  2. 1Introduction
  3. 2Device Nomenclature
  4. 3Device Markings
  5. 4Advisory to Silicon Variant / Revision Map
  6. 5Known Design Exceptions to Functional Specifications
    1.     MSS#25
    2.     MSS#27
    3.     MSS#28
    4.     MSS#29
    5.     MSS#30
    6.     MSS#33
    7.     MSS#40
    8. 5.1  MSS#49
    9. 5.2  MSS#53
    10. 5.3  MSS#54
    11. 5.4  MSS#55
    12. 5.5  MSS#56
    13. 5.6  MSS#57
    14. 5.7  MSS#61
    15. 5.8  MSS#62
    16.     MSS#66
    17. 5.9  MSS#67
    18.     MSS#69
    19.     MSS#70
    20. 5.10 ANA#12A
    21.     ANA#37A
    22.     ANA#39
    23.     ANA#43
    24.     ANA#44
    25.     ANA#45
    26.     ANA#46
    27.     ANA#47
    28.     ANA#58
  7.   Trademarks
  8.   Revision History

5.5 MSS#56

CR4 STC Boot Monitor Failure

Revision(s) Affected:

AWR2944P, AWR2E44P, AWR2944-ECO, AWR2E44-ECO, AWR2944LC, AWR2E44LC

Description:

Cortex CR4 STC Boot Monitor Failure is observed in the device.

Workaround(s):

It is recommended to execute a sequence (MSS_CTRL:MSS_PBIST_KEY_RST[3:0] = 0) to clear the PBIST registers before starting CR4 (BSS) execution in the Secondary boot loader (SBL). Refer to the SBL example code provided by TI.