SWRZ099B April   2020  – March 2022 AWR6843AOP

 

  1. 1Introduction
  2. 2Device Nomenclature
  3. 3Device Markings
  4. 4Usage Notes
    1. 4.1 MSS: SPI Speed in 3-Wire Mode Usage Note
  5. 5Advisory to Silicon Variant / Revision Map
  6. 6Known Design Exceptions to Functional Specifications
    1.     MSS#25
    2.     MSS#26
    3.     MSS#27
    4.     MSS#28
    5.     MSS#29
    6.     MSS#30
    7.     MSS#31
    8.     MSS#32
    9.     MSS#33
    10.     MSS#34
    11.     MSS#36
    12.     MSS#37B
    13.     MSS#38A
    14.     MSS#39
    15.     MSS#40
    16.     MSS#41
    17.     MSS#42A
    18.     MSS#43A
    19.     MSS#44A
    20.     MSS#45
    21. 6.1 MSS#50
    22. 6.2 MSS#51
    23.     ANA#11B
    24.     ANA#12A
    25.     ANA#13B
    26.     ANA#14
    27.     ANA#16
    28.     ANA#17A
    29.     ANA#18B
    30.     ANA#19
    31.     ANA#20
    32.     ANA#22A
    33.     ANA#27A
    34.     ANA#30
    35.     ANA#31
    36.     PACKAGE#02
  7. 7Trademarks
  8. 8Revision History

MSS#37B

DCC Module Frequency Comparison can Report Erroneous Results

Revision(s) Affected:

AWR6843AOP ES2.0

Description:

The Dual-clock Comparator module, which is used to monitor a clock frequency while comparing with a known clock reference, could stop earlier than expected, and, thus, indicating the measured clock frequency to be lower. This is due to a clock domain crossing issue causing a preset to the error detection logic to get triggered.

Workaround(s):

Multiple measurements can be taken for the same clock pairs and abnormal frequencies reported can be ignored

Application code, where possible, could compare the clocks using an alternate clock comparator module (CCC).