SWRZ072B May   2017  – December 2020 AWR1642

 

  1. 1Introduction
  2. 2Device Nomenclature
  3. 3Device Markings
  4. 4Usage Notes
    1. 4.1 MSS: SPI Speed in 3-Wire Mode Usage Note
  5. 5Advisory to Silicon Variant / Revision Map
  6. 6Known Design Exceptions to Functional Specifications
    1.     MSS#10
    2.     MSS#11
    3.     MSS#12
    4.     MSS#14
    5.     MSS#16
    6.     MSS#17
    7.     MSS#18
    8.     MSS#19
    9.     MSS#20
    10.     MSS#22
    11.     MSS#37B
    12.     MSS#38A
    13.     MSS#39
    14.     MSS#40
    15.     MSS#42
    16.     MSS#43
    17.     MSS#44
    18.     MSS#45
    19.     ANA#06
    20.     ANA#08A
    21.     ANA#09A
    22.     ANA#10A
    23.     ANA#11A
    24.     ANA#12A
    25.     ANA#15
    26.     ANA#16
    27.     ANA#17A
    28.     ANA#18B
    29.     ANA#20
    30.     ANA#21A
    31.     ANA#22A
    32.     ANA#24A
    33.     ANA#27
    34.     DSS#01
    35.     DSS#02
    36.     DSS#03
    37.     DSS#04
    38.     DSS#05
    39.     DSS#06
    40.     DSS#07
  7. 7Trademarks
  8. 8Revision History

MSS#37B

DCC Module Frequency Comparison can Report Erroneous Results

Revision(s) Affected:

AWR1642 ES1.0 and AWR1642 ES2.0

Description:

The Dual-clock Comparator module, which is used to monitor a clock frequency while comparing with a known clock reference, could stop earlier than expected, and, thus, indicating the measured clock frequency to be lower. This is due to a clock domain crossing issue causing a preset to the error detection logic to get triggered.

Workaround(s):

Multiple measurements can be taken for the same clock pairs and abnormal frequencies reported can be ignored

Application code, where possible, could compare the clocks using an alternate clock comparator module (CCC).