Introduction

Field programmable gate arrays (FPGAs) are sophisticated and powerful processors. To fully utilize the advantages of advanced semiconductor process technology and maintain a high level of performance, several new FPGAs require an optimized power management approach and voltage. Designers need to consider the power consumption for each rail and design the circuit board using a point-of-load design that incorporates the features needed to provide a practical voltage to each rail. This article briefly introduces several DC/DC controllers, converters and power modules that support Altera® FPGAs requiring Smart voltage identification (SmartVID) and provide an optimized power management approach.

SmartVID

Certain Altera, Agilex™, and Stratix™ FPGAs containing a unique orderable part number suffix are manufactured with an precisely calibrated voltage needed for best performance. With SmartVID, the switching regulator dynamically adjusts the supply voltage rails to the FPGA, accounting for process variations and optimizing the performance of the processor. Please consult Altera documentation to determine which FPGA orderable part number (OPN) requires SmartVID. Specific commands are required by SmartVID within the PMBus interface, depending on the FPGA family.

• VOUT_MODE: determines the format of the VOUT related commands
• VOUT_COMMAND: adjusts the output voltage
• READ_VOUT: verifies the output voltage
• STATUS_BYTE: returns the voltage regulator status
• CLEAR_FAULTS: clears any fault bits

SmartVID requires certain PMBus features to be supported by the firmware of the FPGA vendor.

• PMBus revision 1.3 or later
• 100kHz and 400kHz clock speeds
• Supports a 7-bit address
• Configurable under and over voltage and under and over current settings
• Direct or linear mode operation
• Configurable power-on voltage for the specific FPGA
• Operational without a vendor-specific command (for example, password, write-protect)

Suggested Voltage Regulators for PMBus for SmartVID

Control Architecture

Current mode control is an excellent choice for applications benefiting from a predictable switching frequency. Current mode-controlled devices in the table integrate an oscillator that can be synchronized to an external frequency, making this control architecture an excellent choice for applications using noise-sensitive analog front ends (AFE) and other analog circuitry. D-CAP4 is the latest version of constant on-time architecture that allows a faster transient response time and tighter over and under output voltage overshoot with less output capacitance. D-CAP+ is another derivative of a constant on-time architecture for a fast transient response and used when true current sensing is required in multi-phase applications benefiting from droop compensation (load-line) to further reduce output voltage over and under shoot.

SmartVID versus SVID

Although the abbreviations are somewhat similar, Smart voltage identification (SmartVID) is different than serial voltage identification (SVID). SVID is a proprietary interface for Intel’s Xeon® scalable processor family utilizing an additional digital interface and unique registers, alert, clock, and bidirectional data pins. SVID has a much faster clock frequency than PMBus for SmartVID, allowing the processor to react more quickly to any thermal, voltage, power draw, or fault conditions. Small adjustments in the voltage are made in real-time to balance the performance and power consumption trade-offs. Because many switching regulators with SVID also incorporate a PMBus interface, SVID regulators can still be used in SmartVID applications, but special attention is needed because pin-strap capability can be reduced to maintain lower device pin count, meaning the configuration of the switching regulator can only be allowed using serial PMBus commands. The TPS544B27W is an example of a DC/DC converter with SVID incorporating both a PMBus interface and SVID Bus.

Resources

• Altera SmartVID debug checklist and voltage regulator guidelines.
• Texas Instruments, Control-mode quick reference guide, analog design journal.