SPRZ426E November 2014 – February 2021 DRA710 , DRA712 , DRA714 , DRA716 , DRA718 , DRA722 , DRA724 , DRA725 , DRA726
Ethernet RMII Interface RMII_MHZ_50_CLK Not Supported as Output Reference Clock
High
The Ethernet EMAC module when operating in RMII mode has two clocking modes. In one case, a clock is generated externally and is an input to the SoC via the RMII_MHZ_50_CLK pin. This mode of operation functions properly and the timing specified in the Data Manual is valid.
In the second case, the SoC drives a 50 MHz clock as an output on the RMII_MHZ_50_CLK pin. This output drives the clock to the external PHY. This mode of operation does not meet the timing specified in the Data Manual; and the resulting timing is not compatible with the RMII standard.
When using either of the Ethernet ports in RMII mode (pins rmii0* or rmii1*) the RMII_MHZ_50_CLK signal must be configured as an input, and the clock must be generated external to the SoC. The internal clock generation mode is not supported.
The following registers should be set to configure RMII_MHZ_50_CLK as an input:
CM_GMAC_GMAC_CLKCTRL[CLKSEL_REF] = 1
CTRL_CORE_SMA_SW_6[RMII_CLK_SETTING] = 1
Alternatively, the Ethernet EMAC module supports MII or RGMII protocols/pins on both ports. Those modes can be used if the selected PHY supports them. The typical clocking modes for those interfaces are able to meet the timing specified in the Data Manual for 100 Mbps operation (which is the rate supported by RMII).
DRA72x SR 2.0, 1.0
DRA71x SR 2.1, 2.0
DRA79x: 2.1, 2.0
TDA2Ex (23mm): 2.0, 1.0
TDA2Ex (17mm): 2.1, 2.0
AM571x: 2.1, 2.0, 1.0
AM570x: 2.1, 2.0
DRA72x: 2.0, 1.0
DRA71x: 2.1, 2.0