CRITICALITY

Low

DESCRIPTION

Per the standard, the 'Envelope detector' in the USB2.0 PHY must indicate High Speed disconnection when the amplitude of the differential signal at the downstream facing driver's connector is greater than or equal to 625 mV, and it must not be indicated when the signal amplitude is less than or equal to 525 mV at our connector. The default configuration of the USB1/USB2 phy is such that the detector circuit is monitoring the during the entire SOF frame and not just the last 8b portion of the extended EOP as indicated in the standard.

Due to this constant monitoring, it is possible that the PHY may falsely indicate disconnect condition due to reflections on the PCB. These reflections could exceed the disconnect thresholds if TI PCB layout guidelines for USB are not strictly followed.

WORKAROUND

SW Workaround: During USB2.0 PHY initialization, configure: bit 31 of 0x4A08 404C (USB1) or 0x4A08 504C (USB2) to =1b. This will limit detection window to the proper time and prevent false disconnect. TI PCB layout guidelines for USB should also be strictly followed to minimize reflections to within the thresholds defined in the standard. See device Data Manual for details.

REVISIONS IMPACTED

DRA72x SR 2.0, 1.0
DRA71x SR 2.1, 2.0

DRA79x: 2.1, 2.0

TDA2Ex (23mm): 2.0, 1.0

TDA2Ex (17mm): 2.1, 2.0

AM571x: 2.1, 2.0, 1.0

AM570x: 2.1, 2.0

DRA72x: 2.0, 1.0

DRA71x: 2.1, 2.0