SPRADL7 July 2025 F28E120SC
The Event-Trigger Submodule register differences between EPWM and MCPWM are listed in Table 8-1.
|
EPWM |
MCPWM |
Description |
|---|---|---|
|
ETCLR.INT |
INTCLR.INT |
Clear Interrupt bit register renamed |
|
INTCLR.ET1 |
New interrupt status clear bits for ET1 |
|
|
INTCLR.ET2 |
New interrupt status clear bits for ET2 |
|
|
INTCLR.CNT_OVF |
New interrupt status clear bits for TBCTR overflow |
|
|
INTCLR.CBC |
New interrupt status clear bits for CBC trip |
|
|
INTCLR.OST |
New interrupt status clear bits for one-shot trip |
|
|
ETCLR.SOCA |
SOCCLR.SOCA |
New Register for clearing SOCx events |
|
ETCLR.SOCB |
SOCCLR.SOCB |
New Register for clearing SOCx events |
|
SOCCLR.SOCC |
New Register for clearing SOCx events |
|
|
SOCCLR.SOCD |
New Register for clearing SOCx events |
|
|
ETCNTINIT.INTINIT |
- |
Prescaler custom init value feature removed |
|
ETCNTINIT.SOCAINIT |
- |
Prescaler custom init value feature removed |
|
ETCNTINIT.SOCBINIT |
- |
Prescaler custom init value feature removed |
|
ETCNTINITCTL.INTINITEN |
- |
Prescaler custom init value feature removed |
|
ETCNTINITCTL.INTINITFRC |
- |
Prescaler custom init value feature removed |
|
ETCNTINITCTL.SOCAINITEN |
- |
Prescaler custom init value feature removed |
|
ETCNTINITCTL.SOCAINITFRC |
- |
Prescaler custom init value feature removed |
|
ETCNTINITCTL.SOCBINITEN |
- |
Prescaler custom init value feature removed |
|
ETCNTINITCTL.SOCBINITFRC |
- |
Prescaler custom init value feature removed |
|
ETFLG.INT |
INTFLAG.INT |
Register rename (INTFLAG) |
|
INTFLAG.CBC |
New flag bit for CBC interrupt |
|
|
INTFLAG.CNT_OVF |
New flag bit for TBCTL overflow interrupt |
|
|
INTFLAG.ET1 |
New flag bit for ET1 interrupt |
|
|
INTFLAG.ET2 |
New flag bit for ET2 interrupt |
|
|
INTFLAG.OST |
New flag bit for OST interrupt |
|
|
ETFLG.SOCA |
SOCFLAG.SOCA |
New register for SOCx flags |
|
ETFLG.SOCB |
SOCFLAG.SOCB |
New register for SOCx flags |
|
SOCFLAG.SOCC |
New register for SOCx flags |
|
|
SOCFLAG.SOCD |
New register for SOCx flags |
|
|
ETFRC.INT |
- |
Global interrupt force removed |
|
ETFRC.SOCA |
- |
SOCA force removed |
|
ETFRC.SOCB |
- |
SOCB force removed |
|
ETINTPS.INTCNT2 |
- |
Expanded prescaler counter removed |
|
ETINTPS.INTPRD2 |
- |
Expanded prescaler period removed |
|
ETPS.INTCNT |
- |
Event Trigger INT separated into ET1 and ET2 |
|
ETCNT.ET1_CNT |
Event Trigger INT separated into ET1 and ET2 |
|
|
ETCNT.ET2_CNT |
Event Trigger INT separated into ET1 and ET2 |
|
|
ETPS.INTPRD |
- |
Event Trigger INT separated into ET1 and ET2 |
|
ETPERIOD.ET1_PERIOD |
Event Trigger INT separated into ET1 and ET2 |
|
|
ETPERIOD.ET2_PERIOD |
Event Trigger INT separated into ET1 and ET2 |
|
|
ETPS.INTPSSEL |
- |
Expanded prescaler counter removed |
|
ETPS.SOCACNT |
SOCCNT.SOCA_CNT |
Register rename |
|
ETPS.SOCAPRD |
SOCPERIOD.SOCA_PERIOD |
Register rename |
|
ETPS.SOCBCNT |
SOCCNT.SOCB_CNT |
Register rename |
|
ETPS.SOCBPRD |
SOCPERIOD.SOCB_PERIOD |
Register rename |
|
SOCCNT.SOCC_CNT |
Additional SOCC prescaler counter |
|
|
SOCCNT.SOCD_CNT |
Additional SOCD prescaler counter |
|
|
SOCPERIOD.SOCC_PERIOD |
Additional SOCC prescaler counter |
|
|
SOCPERIOD.SOCD_PERIOD |
Additional SOCD prescaler counter |
|
|
ETPS.SOCPSSEL |
- |
Expanded prescaler counter removed |
|
ETSEL.INTEN |
- |
Event Trigger INT separated into ET1 and ET2 |
|
ETSEL.INTSEL |
- |
Event Trigger INT separated into ET1 and ET2 |
|
INTEN.CBC |
New en bit for CBC interrupt |
|
|
INTEN.CNT_OVF |
New en bit for TBCTL overflow interrupt |
|
|
INTEN.ET1 |
New en bit for ET1 interrupt |
|
|
INTEN.ET2 |
New en bit for ET2 interrupt |
|
|
INTEN.OST |
New en bit for OST interrupt |
|
|
ETSEL.ET1_SEL |
Event Trigger INT separated into ET1 and ET2 |
|
|
ETSEL.ET2_SEL |
Event Trigger INT separated into ET1 and ET2 |
|
|
ETSEL.INTSELCMP |
- |
EPWMxINT Compare Select |
|
ETSEL.SOCAEN |
SOCEN.SOCA_ENABLE |
Start of Conversion A Enable |
|
ETSEL.SOCASEL |
SOCSEL.SOCA_SEL |
Start of Conversion A Select |
|
ETSEL.SOCASELCMP |
- |
Not needed since SOCC and SOCD events are independent events |
|
ETSEL.SOCBEN |
SOCEN.SOCB_ENABLE |
Register rename |
|
ETSEL.SOCBSEL |
SOCSEL.SOCB_SEL |
Register rename |
|
ETSEL.SOCBSELCMP |
- |
Not needed since SOCC and SOCD events are independent events |
|
SOCEN.SOCC_ENABLE |
New SOCC and SOCD events |
|
|
SOCEN.SOCD_ENABLE |
New SOCC and SOCD events |
|
|
SOCSEL.SOCC_SEL |
New SOCC and SOCD events |
|
|
SOCSEL.SOCD_SEL |
New SOCC and SOCD events |
|
|
ETSOCPS.SOCACNT2 |
- |
Expanded prescaler counter removed |
|
ETSOCPS.SOCAPRD2 |
- |
Expanded prescaler counter removed |
|
ETSOCPS.SOCBCNT2 |
- |
Expanded prescaler counter removed |
|
ETSOCPS.SOCBPRD2 |
- |
Expanded prescaler counter removed |
|
- |
INTFRC.CBC |
Independent software force bits for each interrupt source |
|
- |
INTFRC.CNT_OVF |
Independent software force bits for each interrupt source |
|
- |
INTFRC.ET1 |
Independent software force bits for each interrupt source |
|
- |
INTFRC.ET2 |
Independent software force bits for each interrupt source |
|
- |
INTFRC.OST |
Independent software force bits for each interrupt source |