SPRADL7 July 2025 F28E120SC
The register differences for the Time-Base Submodule between EPWM and MCPWM are listed in Table 3-1.
|
EPWM |
MCPWM |
Description |
|---|---|---|
|
TBCTL2.OSHTSYNC |
- |
One-shot Sync Out Feature Removed on MCPWM |
|
TBCTL2.OSHTSYNCMODE |
- |
One-shot sync out feature removed on MCPWM |
|
TBCTL2.PRDLDSYNC |
- |
Shadow loading of period on SYNC input pulse removed on MCPWM |
|
TBCTL3.OSSFRCEN |
- |
One-shot sync out feature removed on MCPWM |
|
TBPHS.TBPHSHR |
- |
HRPWM not present on MCPWM |
|
TBSTS.CTRMAX |
- |
CTRMAX flag removed on MCPWM |
|
TBCTL.HSPCLKDIV |
TBCTL.CLKDIV |
High Speed TBCLK Pre-scaler |
|
TBCTL.SWFSYNC |
TBCTL.SWSYNC |
Bitfield name change |
|
SYNCINSEL.SEL |
TBCTL.SYNCISEL |
Dedicated SYNC input select register combined into TBCTL register, refer to TBCTL register description. |
|
SYNCOUTEN.CMPBEN |
TBCTL.SYNCOSEL |
Dedicated SYNC input select register combined into TBCTL register, refer to TBCTL register description. |
|
SYNCOUTEN.CMPCEN |
TBCTL.SYNCOSEL |
Dedicated SYNC input select register combined into TBCTL register, refer to TBCTL register description. |
|
SYNCOUTEN.CMPDEN |
TBCTL.SYNCOSEL |
Dedicated SYNC input select register combined into TBCTL register, refer to TBCTL register description. |
|
SYNCOUTEN.DCAEVT1EN |
TBCTL.SYNCOSEL |
Dedicated SYNC input select register combined into TBCTL register, refer to TBCTL register description. |
|
SYNCOUTEN.DCBEVT1EN |
TBCTL.SYNCOSEL |
Dedicated SYNC input select register combined into TBCTL register, refer to TBCTL register description. |
|
SYNCOUTEN.SWEN |
TBCTL.SYNCOSEL |
Dedicated SYNC input select register combined into TBCTL register, refer to TBCTL register description. |
|
SYNCOUTEN.ZEROEN |
TBCTL.SYNCOSEL |
Dedicated SYNC input select register combined into TBCTL register, refer to TBCTL register description. |
|
HRPCTL.PWMSYNCSEL |
TBCTL.SYNCPERSEL |
SYNCPER control moved from HRPCTL register to TBCTL register |
|
- |
TBPRDS.TBPRDS |
Addition of memory-mapped TBPRD shadow register |
|
- |
TBSTSCLR.SYNCI |
Addition of separate register for clearing SYNC input status bit |