SPRAD64 November   2022 AM620-Q1 , AM623 , AM625 , AM625-Q1

 

  1.   Trademarks
  2. 1 Introduction
  3. 2 Width/Spacing Proposal for Escapes
  4. 3 Stackup
  5. 4 Via Sharing
  6. 5 Floorplan Component Placement
  7. 6 Critical Interfaces Impact Placement
  8. 7 Routing Priority
  9. 8 SerDes Interfaces
  10. 9 DDR Interfaces
  11. 10Power Decoupling
  12. 11Route Lowest Priority Interfaces Last
  13. 12Summary

8 SerDes Interfaces

The package BGA ball map is also arranged to support routing the highest priority interfaces first. Therefore, the SerDes CSI interfaces are located close to the outer rings. The lanes located on the outermost row of BGAs can be escaped on the top layer. The lanes located on inner BGA rows require vias to escape as a differential pair on the bottom or on an interior layer. The BGA map facilitates this for inner rows. See Figure 8-1 for an example of the SerDes signals on the AM62x AMC board on the top layer and on an inner layer. Wide traces can limit the signal loss but could violate the impedance requirements. For more detailed information on routing Serdes signals, refer to High-Speed Interface Layout Guidelines.

GUID-75DBBFD9-8478-466B-8BD6-D195567F9F15-low.png Figure 8-1 Serdes CSI Escapes for TOP layer (Left) and Inner layer (Right)