SPRAD13 May   2022 AM623 , AM625

 

  1.   Abstract
  2.   Trademarks
  3. 1 Introduction
  4. 2 Via Channel Arrays
  5. 3 Width/Spacing Proposal for Escapes
  6. 4 Stackup
  7. 5 Via Sharing
  8. 6 Floorplan Component Placement
  9. 7 Critical Interfaces Impact Placement
  10. 8 Routing Priority
  11. 9 SerDes Interfaces
  12. 10DDR Interfaces
  13. 11Power Decoupling
  14. 12Route Lowest Priority Interfaces Last
  15. 13Summary

12 Route Lowest Priority Interfaces Last

When the length matching and simulations have been completed for the highest priority interfaces and the Power Distribution Network (PDN) analysis has been completed, then the layout can continue with the medium, then the lower priority interfaces.