SPRAD13 May   2022 AM623 , AM625

 

  1.   Abstract
  2.   Trademarks
  3. 1 Introduction
  4. 2 Via Channel Arrays
  5. 3 Width/Spacing Proposal for Escapes
  6. 4 Stackup
  7. 5 Via Sharing
  8. 6 Floorplan Component Placement
  9. 7 Critical Interfaces Impact Placement
  10. 8 Routing Priority
  11. 9 SerDes Interfaces
  12. 10DDR Interfaces
  13. 11Power Decoupling
  14. 12Route Lowest Priority Interfaces Last
  15. 13Summary

5 Via Sharing

The Via Channel Array BGA pattern implemented on the AM62 design offers several opportunities for via sharing. Vias are shared across BGA pins. Figure 5-1 and Figure 5-2 show the via sharing opportunities for VDDR_CORE and VSS domains, respectively. Figure 5-1 assumes that VDD_CORE and VDDR_CORE domains are separate. If these domains are merged, more via sharing opportunities are presented, as shown in Figure 5-3. Via sharing across BGA pins provides for easier escape routing and also stronger electrical connections by connecting multiple pins.

GUID-20211214-SS0I-PCHG-DWK9-5P2DRQH5HLJZ-low.png Figure 5-1 Via Sharing for VDDR_CORE Domain
GUID-20211214-SS0I-5GKK-HWFG-V2Q9JLSRJQZP-low.png Figure 5-2 Via Sharing for VSS
GUID-20211214-SS0I-H3D0-QMGN-3BWSCW88PWVW-low.png Figure 5-3 Via Sharing for Merged VDD_CORE and VDDR_CORE Domains