SPRAAU8A March   2008  – August 2017 TMS320F2801 , TMS320F2801 , TMS320F2801-Q1 , TMS320F2801-Q1 , TMS320F28015 , TMS320F28015 , TMS320F28016 , TMS320F28016 , TMS320F28016-Q1 , TMS320F28016-Q1 , TMS320F2802 , TMS320F2802 , TMS320F2802-Q1 , TMS320F2802-Q1 , TMS320F28044 , TMS320F28044 , TMS320F2806 , TMS320F2806 , TMS320F2806-Q1 , TMS320F2806-Q1 , TMS320F28062 , TMS320F28062 , TMS320F28062-Q1 , TMS320F28062-Q1 , TMS320F28062F , TMS320F28062F , TMS320F28062F-Q1 , TMS320F28062F-Q1 , TMS320F28063 , TMS320F28063 , TMS320F28064 , TMS320F28064 , TMS320F28065 , TMS320F28065 , TMS320F28066 , TMS320F28066 , TMS320F28066-Q1 , TMS320F28066-Q1 , TMS320F28067 , TMS320F28067 , TMS320F28067-Q1 , TMS320F28067-Q1 , TMS320F28068F , TMS320F28068F , TMS320F28068M , TMS320F28068M , TMS320F28069 , TMS320F28069 , TMS320F28069-Q1 , TMS320F28069-Q1 , TMS320F28069F , TMS320F28069F , TMS320F28069F-Q1 , TMS320F28069F-Q1 , TMS320F28069M , TMS320F28069M , TMS320F28069M-Q1 , TMS320F28069M-Q1 , TMS320F2808 , TMS320F2808 , TMS320F2808-Q1 , TMS320F2808-Q1 , TMS320F2809 , TMS320F2809 , TMS320F2810 , TMS320F2810 , TMS320F2810-Q1 , TMS320F2810-Q1 , TMS320F2811 , TMS320F2811 , TMS320F2811-Q1 , TMS320F2811-Q1 , TMS320F2812 , TMS320F2812 , TMS320F2812-Q1 , TMS320F2812-Q1 , TMS320F28232 , TMS320F28232 , TMS320F28232-Q1 , TMS320F28232-Q1 , TMS320F28234 , TMS320F28234 , TMS320F28234-Q1 , TMS320F28234-Q1 , TMS320F28235 , TMS320F28235 , TMS320F28235-Q1 , TMS320F28235-Q1 , TMS320F28332 , TMS320F28332 , TMS320F28333 , TMS320F28333 , TMS320F28334 , TMS320F28334 , TMS320F28335 , TMS320F28335 , TMS320F28335-Q1 , TMS320F28335-Q1

 

  1.   Copying Compiler Sections From Flash to RAM on the TMS320F28xxx DSCs
    1.     Trademarks
    2. 1 Introduction
    3. 2 Compiler Sections
    4. 3 Software
      1. 3.1 Description
        1. 3.1.1 Code_start and wd_disable
        2. 3.1.2 Copy_sections
        3. 3.1.3 Memory Allocation – Linker Command Files
      2. 3.2 Testing Example
        1. 3.2.1 Code Composer Studio Environment
        2. 3.2.2 Standalone Operation
      3. 3.3 Application Integration
        1. 3.3.1 Example Integration
    5. 4 Benchmarks, Limitations, and Suggestions
      1. 4.1 Memory Usage
      2. 4.2 Benchmarks
      3. 4.3 Limitations
      4. 4.4 Suggestions
    6. 5 Conclusion
    7. 6 References
  2.   Revision History

4.2 Benchmarks

Since this functionality is implemented directly after boot, the Flash wait states and phase-locked loop (PLL) are not configured and, therefore, run at their default values. The Flash wait states are configured for 15 cycles and SYSCLKOUT of OSCCLK/2 for the F280xx/F281x devices and OSCCLK/4 for F2833x devices. Using the profiling feature of Code Composer Studio, the execution time can be measured. Table 3 shows the timing information for each F28xxx DSC by measuring the time elapsed from boot to the first instruction within the main( ) function for the examples provided in the associated code files. As shown, the execution time for each platform increases; this is due to an increase in code size and decreasing SYSCLKOUT.

Table 3. Execution Time

OSCCLK (MHz) SYSCLKOUT (MHz) Cycles Execution Time (ms)
TMS320F2812 30 15 18,576 1.238
TMS320F2808 20 10 20,560 2.056
TMS320F28335 30 7.5 29,681 3.957