SNVU755A January   2021  – June 2021 TLV841

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Related Documentation
    2. 1.2 TLV841 Applications
  3. 2Schematic, Bill of Materials, and Layout
    1. 2.1 TLV841EVM Schematic
    2. 2.2 TLV841EVM Bill of Materials
    3. 2.3 Layout and Component Placement
    4. 2.4 Layout
  4. 3EVM Connectors
    1. 3.1 EVM Test Points
    2. 3.2 EVM Jumpers
  5. 4EVM Setup and Operation
    1. 4.1 Input Power (VDD)
    2. 4.2 Monitoring Voltage on SENSE Pin (TLV841S)
    3. 4.3 Monitoring Voltage on VDD (TLV841M and TLV841C)
    4. 4.4 Manual Reset (MR) (TLV841M)
    5. 4.5 Reset Output (RESET)
    6. 4.6 Reset Time Delay Programming (Program tD via CT) (TLV841C)
  6. 5Revision History

4.2 Monitoring Voltage on SENSE Pin (TLV841S)

The TLV841S device variant option monitors the voltage via the SENSE pin. The user can connect to the SENSE pin using TP3. The TLV841EVM provides two options for voltage monitoring.

1. Monitor VDD: VDD can be monitored by connecting the shunt to jumper J4 which creates a short and makes Vmon = VDD

2. Voltage divider for Vmon: Vmon connects to the SENSE pin through a voltage divider. To use this voltage divider, connect the shunt to jumper J8 (pin 3 [Rdiv] to pin 2 [GND]). This voltage divider can be adjusted to monitor any voltage above the VIT-, which is 0.505 V, for the default device TL841SADL01YBHR.
(See Table 4-1 for information on the default EVM threshold voltage values.)

OPTIONAL: Although not required in most cases, for noisy applications, the TLV841EVM contains jumper J6 (Jumper J6 is meant for TLV841C option) that allows the user the flexibility to add a bypass capacitor C2 or C3 on the SENSE input. Adding a bypass capacitor at the SENSE input will help reduce the sensitivity to transient voltages on the monitored signal but affect the timing specs such as increasing the reset time delay tD.

Table 4-1 Nominal Input Threshold Voltage
DEVICE VIT- VIT+ Vmon NEGATIVE-GOING THRESHOLD VOLTAGE Vmon POSITIVE-GOING THRESHOLD VOLTAGE
TLV841SADL01,
R1 = 47.5 kΩ, R2 = 10 kΩ
(x0.174 Voltage Divider Ratio)		 0.505 V 0.530 V 2.90 V 3.05 V

Upon start-up, the TLV841 requires VDD to be above VPOR = 0.7 V before the RESET output is in the correct logic state. The TLV841 has built-in glitch immunity so voltage transients on VDD or SENSE are ignored if the pulse duration is 10 µs or less as shown in Figure 4-1. The glitch immunity specification depends on the amplitude of the voltage transient and the operating conditions. Please see the Glitch Immunity specification in the Timing Requirements section of the TLV841 datasheet for more detailed information.

Figure 4-1 TLV841EVM Glitch Immunity