SNLA404 December   2022 DP83TC811R-Q1 , DP83TC811S-Q1 , DP83TC812R-Q1 , DP83TC812S-Q1 , DP83TG720R-Q1 , DP83TG720S-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2PHY Link-up Sequence
    1. 2.1 Microcontroller Initialization
    2. 2.2 Power-up Sequence
      1. 2.2.1 All Supplies Ramped
      2. 2.2.2 PHY Clock Required Good
      3. 2.2.3 SMI Access Available
      4. 2.2.4 PHY Bootstraps Sampled
    3. 2.3 Check Device ID
    4. 2.4 PHY Initialization
      1. 2.4.1 Managed or Autonomous Mode?
      2. 2.4.2 Program PHY Configuration Settings, Enable Link Start-up
      3. 2.4.3 Program PHY Into Autonomous Mode
      4. 2.4.4 Soft Restart or Polling for Link
      5. 2.4.5 Results of Link Polling
    5. 2.5 Post Start-up Operation
    6. 2.6 Reset Sequence
      1. 2.6.1 Reset Initiated
      2. 2.6.2 SMI Access Available
      3. 2.6.3 Transition to Normal Operation
  5. 3Summary
  6.   A Appendix

2.2.3 SMI Access Available

At TB (relative to T0), the PHY is able to be accessible via SMI access. MDC and MDIO are used for this communication.

811

720

812
TB (ms)

60

60

60

Figure 2-4 shows the MDC and MDIO timing diagram. The pairs are separated as the write timing diagram is above the read diagram. Within the pairs, MDC is above MDIO. Please be aware that some PHYs can require 32 bits of preamble for the synchronization purposes.

Figure 2-4 SMI Timing