SNLA404 December   2022 DP83TC811R-Q1 , DP83TC811S-Q1 , DP83TC812R-Q1 , DP83TC812S-Q1 , DP83TG720R-Q1 , DP83TG720S-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2PHY Link-up Sequence
    1. 2.1 Microcontroller Initialization
    2. 2.2 Power-up Sequence
      1. 2.2.1 All Supplies Ramped
      2. 2.2.2 PHY Clock Required Good
      3. 2.2.3 SMI Access Available
      4. 2.2.4 PHY Bootstraps Sampled
    3. 2.3 Check Device ID
    4. 2.4 PHY Initialization
      1. 2.4.1 Managed or Autonomous Mode?
      2. 2.4.2 Program PHY Configuration Settings, Enable Link Start-up
      3. 2.4.3 Program PHY Into Autonomous Mode
      4. 2.4.4 Soft Restart or Polling for Link
      5. 2.4.5 Results of Link Polling
    5. 2.5 Post Start-up Operation
    6. 2.6 Reset Sequence
      1. 2.6.1 Reset Initiated
      2. 2.6.2 SMI Access Available
      3. 2.6.3 Transition to Normal Operation
  5. 3Summary
  6.   A Appendix

2.6.1 Reset Initiated

The PHY is sent into the reset state. This can be done in two ways, via hardware where the Reset pin is held low for F duration, or via software where register 0x1F[15] = ‘1’. The point in time when either the Reset pin is released, or the write command has been delivered to the PHY is known as T1. While these procedures do initiate a reset of the PHY, issuing the reset via pin toggling causes the PHY to sample the bootstraps while issuing a via register write does not cause resampling.

811

720

812
Reset pin held low to initiate (µs)

1

65

0.72