SNLA340 October   2022 DP83TC811R-Q1 , DP83TC811S-Q1 , DP83TC812R-Q1 , DP83TC812S-Q1 , DP83TC814R-Q1 , DP83TC814S-Q1 , DP83TG720R-Q1 , DP83TG720S-Q1

 

  1.   DP83TC811, DP83TC812, DP83TC814, DP83TG720 Hardware Rollover Document
  2.   Trademarks
  3. 1Introduction
  4. 2Device Comparison
    1. 2.1 Pin Map Comparison
      1. 2.1.1 DP83TC811S
      2. 2.1.2 DP83TC811R
      3. 2.1.3 DP83TC812S
      4. 2.1.4 DP83TC812R
      5. 2.1.5 DP83TC814S
      6. 2.1.6 DP83TC814R
      7. 2.1.7 DP83TG720S
      8. 2.1.8 DP83TG720R
    2. 2.2 Feature Comparison
    3. 2.3 Pin Comparison Table
      1. 2.3.1 Strap Comparison
        1. 2.3.1.1 PHY Address Straps
        2. 2.3.1.2 MAC Interface, Master/Slave, Autonomous Strap
    4. 2.4 Power Supply Comparison
    5. 2.5 Design Parameters
    6. 2.6 MDI Comparison
    7. 2.7 CMC Comparison
    8. 2.8 SGMII Reference Schematics
    9. 2.9 RGMII Reference Schematics
  5. 3Summary

2.3.1.2 MAC Interface, Master/Slave, Autonomous Strap

Strap features on RX_D0, RX_D1, RX_D2, LED_0, and LED_1 are same for all four devices. They can be used by keeping the strap resistors open or by using a pull up resistor. Test Mode straps are not supported on DP83TC812, DP83TC814, and DP83TG720. This allows those strap pins to be used as two level straps. The PHYs can be configured in Test Modes via register access.

When strap resistors are not used, the PHY's internal pull down resistors will configure the PHY in Mode 1 by default. However, for LED pins it is recommended to use pull down resistor in parallel with the an LED when using Mode 1.

Table 2-6 MAC Interface, Master/Slave, Autonomous Strap Comparison Table
PIN NO. PIN NAME DP83TC811 DP83TC812, DP83TC814, DP83TG720
STRAP MODE Table 2-7 STRAP STRAP MODE Table 2-8 STRAP
26RX_D0MAC[0]TEST[0]MAC[0]NA
Mode 100Mode 10
Mode 201NANA
Mode 310NANA
Mode 411Mode 21
25RX_D1MAC[1]TEST[1]MAC[1]NA
Mode 100Mode 10
Mode 201NANA
Mode 310NANA
Mode 411Mode 21
24RX_D2MAC[2]TEST[2]MAC[2]NA
Mode 100Mode 10
Mode 201NANA
Mode 310NANA
Mode 411Mode 21
35LED_0MSRESERVEDMSNA
Mode 10Mode 10
Mode 2RESERVEDRESERVEDNANA
Mode 3RESERVEDRESERVEDNANA
Mode 41Mode 21
6LED_1AUTORESERVEDAUTORESERVED
Mode 10Mode 10
Mode 2RESERVEDRESERVEDNANA
Mode 3RESERVEDRESERVEDNANA
Mode 41Mode 21

Table 2-7 shows strap resistor values for DP83TC811 and Table 2-8 shows strap resistor values for DP83TC812, DP83TC814, and DP83TG720.

Table 2-7 Recommended 4-level Strap Resistor Ratios For DP83TC811
MODEIDEAL RH (kΩ)IDEAL RL (kΩ)
1OPENOPEN
2102.49
35.762.49
42.49OPEN
Table 2-8 Recommended 2-level Strap Resistor for DP83TC812/814, DP83TG720
MODEIDEAL RH (kΩ)
1OPEN
22.49
Table 2-9 100BASE-T1 Master and 100BASE-T1 Slave Selection Bootstrap

MS

DESCRIPTION

0

100BASE-T1 Slave Configuration

1

100BASE-T1 Master Configuration
Table 2-10 MAC Interface Selection Bootstraps

MAC[2]

MAC[1]

MAC[0]

DESCRIPTION

0

0

0

SGMII (4-wire)

0

0

1

MII

(DP83TC81x only)

0

1

0

RMII Slave (DP83TC81x only)

0

1

1

RMII Master (DP83TC81x only)

1

0

0

RGMII (Align Mode)

1

0

1

RGMII (TX Internal Delay Mode)

1

1

0

RGMII (TX and RX Internal Delay Mode)

1

1

1

RGMII (RX Internal Delay Mode)
Table 2-11 Test Mode Bootstraps

TEST[2]

TEST[1]

TEST[0]

DESCRIPTION

0

0

0

Normal Operation

0

0

1

Test Mode 1

0

1

0

Test Mode 2

0

1

1

RESERVED

1

0

0

Test Mode 4

1

0

1

Test Mode 5

1

1

0

RESERVED

1

1

1

RESERVED
Table 2-12 Autonomous Mode Bootstrap

AUTO

DESCRIPTION

0

Autonomous Mode, PHY able to establish link after power-up

1

Managed Mode, PHY must be allowed to establish link after power-up based on register write