SNAA366 October   2022 LMX1204

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Basic Clock Distribution System
    2. 1.2 Pre-multiplier Stage
  4. 2Low-Frequency Reference
    1. 2.1 Pre-multiplier Stage
    2. 2.2 LMX1204 Multiplier Stage
    3. 2.3 LMX1204 Multiplier vs RF Synthesizer
  5. 3Real-World Application With AFE7950 RF Sampling Transceiver
    1. 3.1 AFE7950 Clocking Measurement Setup
    2. 3.2 AFE7950 Clocking Measurement Results
  6. 4Conclusion

Real-World Application With AFE7950 RF Sampling Transceiver

The AFE7950 is a 4T6R RF sampling transceiver that is typically used in large phased array systems because of the high frequency of operation and the number of integrated channels available. The AFE7950 clock typically ranges from around 6 GHz up to around 12 GHz. The user determines the clock frequency based on the RF band and power consumption trade-offs. For output bands below 6 GHz, a clock frequency at 6 GHz is likely sufficient and reduces power consumption compared to injecting a higher clock frequency. The DAC clock is taken directly from the sample clock; the ADC clock is divided down from the sample clock and is limited to a max of 3 GHz. The AFE7950 can integrate PLL/VCO to generate the sample clock; however, providing an external clock that has better phase-noise performance is an alternative approach.

Figure 3-1 illustrates a block diagram of a 64T64R phase array system using 16 AFE7950 devices with external clock. Each AFE7950 needs a sample clock. The cascaded LMX1204 topology provides the clock distribution to all of the transceiver devices. The root LMX1204 multiplies the reference signal up to the sample clock frequency. The subsequent LMX1204 stages operate in buffer mode to distribute the signal to each AFE device. Though not depicted in the block diagram, the LMX1204 also provides clocking signals to the FPGA and SYSREF signals to all the devices.

Figure 3-1 AFE7950 64T64R Phased-Array System With Clock Distribution