SLVUDY3 June   2026

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Device Information
  7. 2Hardware
    1. 2.1 Board Overview
      1. 2.1.1 RF Signal Chain
        1. 2.1.1.1 Output Power
      2. 2.1.2 Clocking
      3. 2.1.3 Power
    2. 2.2 Required Equipment
    3. 2.3 Hardware Setup
    4. 2.4 LED Indicators
    5. 2.5 Inputs, Outputs, and Controls
    6. 2.6 USB Interface
  8. 3Software
    1. 3.1 Required Software
    2. 3.2 GUI Installation
  9. 4Implementation Results
    1. 4.1 Evaluation Setup
    2. 4.2 SCPI Control Example
    3. 4.3 Python Scripting Example
    4. 4.4 Power Combining
  10. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials (BOM)
  11. 6Additional Information
    1.     Trademarks

2.1.1 RF Signal Chain

The TSG06D00EVM has two semi-independent RF output channels each with an identical RF signal chain capable of outputing signals from 10MHz to 6GHz with <1nHz frequency resolution.

TSG06D00EVM RF Output Block DiagramFigure 2-1 RF Output Block Diagram

The DDS39RF12 operates in two sample rate modes. Both channels share the same sample clock from the LMX2820, so the mode in use affects both channels.

Table 2-1 Frequency Ranges
Frequency Range Both Channels Independent? Notes
10MHz to 4.8GHz Yes Both channels can operate fully independently when both are in use in the same frequency range.
4.8GHz to 6GHz Yes
Mixed (one channel in each range) With caveats The instrument switches the DAC sample rate to accommodate the new channel frequency. The other channel continues to operate but due to aliasing, image frequencies can be present. The user is responsible for verifying output spectral purity in this configuration.