SLVUDW6B May   2026  – June 2026 TPSM8D7420 , TPSM8D7620

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Setup
      1. 2.1.1 Input and Output Connector Descriptions
      2. 2.1.2 Modification
      3. 2.1.3 Input Capacitor
      4. 2.1.4 Output Capacitor
  8. 3Hardware Design Files
    1. 3.1 Schematic
    2. 3.2 PCB Layout
    3. 3.3 Bill of Materials
  9. 4Additional Information
    1. 4.1 Trademarks
  10. 5Revision History

3.2 PCB Layout

The PCB of the TPSM8D7620EVM has six layers. Figure 3-2 and Figure 3-3 show the top side and bottom side of the PCB layout, respectively. Figure 3-4, Figure 3-5, Figure 3-6, and Figure 3-7 show the inner layer 1 and inner layer 2, inner layer 3, and inner layer 4, respectively.

TPSM8D7620EVM Top-Side Composite ViewFigure 3-2 Top-Side Composite View
TPSM8D7620EVM Bottom-Side Composite ViewFigure 3-3 Bottom-Side Composite View
TPSM8D7620EVM Inner Layer 1 LayoutFigure 3-4 Inner Layer 1 Layout
TPSM8D7620EVM Inner Layer 2 LayoutFigure 3-5 Inner Layer 2 Layout
TPSM8D7620EVM Inner Layer 3 LayoutFigure 3-6 Inner Layer 3 Layout
TPSM8D7620EVM Inner Layer 4 LayoutFigure 3-7 Inner Layer 4 Layout