SLVUCL9 june   2023 TPS65219

 

  1.   1
  2.   ABSTRACT
  3.   Trademarks
  4. 1Introduction
  5. 2EEPROM Device Settings
    1. 2.1  PDN and Sequence Diagrams
      1. 2.1.1 TPS6521907 Sequence and Power Block Diagram
    2. 2.2  Device ID
    3. 2.3  Enable Settings
    4. 2.4  Regulator Voltage Settings
    5. 2.5  Power-Up Sequence Settings
    6. 2.6  Power-Down Sequence Settings
    7. 2.7  EN / PB / VSENSE Settings
    8. 2.8  Multi-Function Pin Settings
    9. 2.9  Over-Current Deglitch
    10. 2.10 Mask Settings
    11. 2.11 Discharge Check
    12. 2.12 Multi PMIC Config

2.1 PDN and Sequence Diagrams

This section breaks out the power sequence settings for the device including the power-up/power-down slot assignment and duration. There may be slots in which no rail nor GPO is assigned to ramp. In this case, we use a combination of slot durations to achieve desired delay times or allow to increase/reduce the timings.