SLVUCL9 june   2023 TPS65219

 

  1.   1
  2.   ABSTRACT
  3.   Trademarks
  4. 1Introduction
  5. 2EEPROM Device Settings
    1. 2.1  PDN and Sequence Diagrams
      1. 2.1.1 TPS6521907 Sequence and Power Block Diagram
    2. 2.2  Device ID
    3. 2.3  Enable Settings
    4. 2.4  Regulator Voltage Settings
    5. 2.5  Power-Up Sequence Settings
    6. 2.6  Power-Down Sequence Settings
    7. 2.7  EN / PB / VSENSE Settings
    8. 2.8  Multi-Function Pin Settings
    9. 2.9  Over-Current Deglitch
    10. 2.10 Mask Settings
    11. 2.11 Discharge Check
    12. 2.12 Multi PMIC Config

2.1.1 TPS6521907 Sequence and Power Block Diagram

GUID-20230123-SS0I-GLPJ-6KZ2-NPRFF2MZRCMP-low.svg Figure 2-1 TPS6521907 Example Power Block Diagram
GUID-20230123-SS0I-GDQF-QBT5-TXR4LDSWGKWW-low.svg Figure 2-2 TPS6521907 Power-Up Sequence
GUID-20230123-SS0I-CJMN-SDT9-C4FQVLZWFTRW-low.svg Figure 2-3 TPS6521907 Power-Down Sequence