SLVUCJ3 February   2023 TPS65220

 

  1.   ABSTRACT
  2.   Trademarks
  3. 1Introduction
  4. 2EEPROM Device Settings
    1. 2.1  Device ID
    2. 2.2  Enable Settings
    3. 2.3  Regulator Voltage Settings
    4. 2.4  Power Sequence Settings
      1. 2.4.1 Power Sequence Settings - Slot assignments
      2. 2.4.2 Power Sequence Settings - Slot Durations
      3. 2.4.3 TPS6522053 Sequence and Power Block Diagram
    5. 2.5  EN / PB / VSENSE Settings
    6. 2.6  Multi-Function Pin Settings
    7. 2.7  Over-Current Deglitch
    8. 2.8  Mask Settings
    9. 2.9  Discharge Check
    10. 2.10 Multi PMIC Config

2.3 Regulator Voltage Settings

This section describes how each of the PMIC power resources were configured.

Table 2-4 Buck Regulator Settings
PMIC RailRegister NameField NameValueDescription
Bucks Switching Mode

(Global for all Buck regulators)

 BUCKS_CONFIG BUCK_FF_ENABLE 0x0 Quasi-fixed frequency mode
BUCKS_CONFIG BUCK_SS_ENABLE 0x0 Spread spectrum disabled
BUCK1BUCK1_VOUTBUCK1_VSET0x60.750V
BUCK1_VOUT BUCK1_UV_THR_SEL 0x0 -5% UV detection level
BUCK1_VOUT BUCK1_BW_SEL 0x1 high bandwidth
BUCK2BUCK2_VOUT BUCK2_VSET0x241.800V
BUCK2_VOUT BUCK2_UV_THR_SEL 0x0 -5% UV detection level
BUCK2_VOUT BUCK2_BW_SEL 0x1 high bandwidth
BUCKS_CONFIG BUCK2_PHASE_CONFIG 0x3 270 degrees (only applicable if Bucks are configured for fixed frequency)
BUCK3BUCK3_VOUTBUCK3_VSET0x141.100V
BUCK3_VOUT BUCK3_UV_THR_SEL 0x0 -5% UV detection level
BUCK3_VOUT BUCK3_BW_SEL 0x1 high bandwidth
BUCKS_CONFIG BUCK3_PHASE_CONFIG 0x2 180 degrees (only applicable if Bucks are configured for fixed frequency)

Note:
  • When Bucks are configured for quasi-fixed frequency (BUCK_FF_ENABLE=0x0), changing the switching mode between auto-PFM and forced-PWM can be triggered by I2C (MODE_I2C_CTRL) or with one of the multi-function pins (MODE/RESET or MODE/STBY) if one of them is configured as MODE. "Forced PWM" has priority over "Auto PFM".
  • "BUCK2_PHASE_CONFIG", "BUCK3_PHASE_CONFIG" and "BUCK_SS_ENABLE" are only applicable when the Buck regulators are configured for fixed frequency (BUCK_FF_ENABLE=0x1).

Table 2-5 LDO Regulator Settings
PMIC Rail Setting Register Name Field Name Value Description
LDO1 LDO1 output voltage LDO1_VOUT LDO1_VSET 0x36 3.300V
LDO1 configuration LDO1_VOUT LDO1_LSW_CONFIG 0x0 Not Applicable (LDO1 not configured as load-switch)
LDO1_VOUT LDO1_BYP_CONFIG 0x1 LDO1 configured as Bypass (only applicable if LDO1_LSW_CONFIG=0x0)
LDO1 UV threshold GENERAL_CONFIG LDO1_UV_THR 0x0 -5% UV detection level (only applicable if configured as LDO)
LDO2 LDO2 output voltage LDO2_VOUT LDO2_VSET 0x5 0.850V / reserved
LDO2 configuration LDO2_VOUT LDO2_LSW_CONFIG 0x0 Not Applicable (LDO2 not configured as load-switch)
LDO2_VOUT LDO2_BYP_CONFIG 0x0 LDO2 configured as LDO (only applicable if LDO2_LSW_CONFIG=0x0)
LDO2 UV threshold GENERAL_CONFIG LDO2_UV_THR 0x0 -5% UV detection level (only applicable if configured as LDO)
LDO3 LDO3 output voltage LDO3_VOUT LDO3_VSET 0x18 1.800V
LDO3 configuration LDO3_VOUT LDO3_LSW_CONFIG 0x0 LDO Mode
LDO ramp configuration LDO3_VOUT LDO3_SLOW_PU_RAMP 0x1 Slow ramp for power-up (~3ms)
LDO3 UV threshold GENERAL_CONFIG LDO3_UV_THR 0x0 -5% UV detection level (only applicable if configured as LDO)
LDO4 LDO4 output voltage LDO4_VOUT LDO4_VSET 0x26 2.500V
LDO3 configuration LDO4_VOUT LDO4_LSW_CONFIG 0x0 LDO Mode
LDO ramp configuration LDO4_VOUT LDO4_SLOW_PU_RAMP 0x1 Slow ramp for power-up (~3ms)
LDO4 UV threshold GENERAL_CONFIG LDO4_UV_THR 0x0 -5% UV detection level (only applicable if configured as LDO)
Note:
  • If a LDO is configured in bypass-mode or LSW-mode, UV-detection is not supported.
  • If an LDO is configured in bypass-mode, the corresponding PVIN_LDOx supply must match the configured output voltage in the LDOx_VOUT register.
  • If LDO is configured as load-switch (LSW_mode), the desired voltage does not need to be configured in the LDOx_VOUT register.
  • In bypass- or LSW-mode, the LDO acts as a switch, where VOUT is VIN minus the drop over the FET-resistance.
  • If LDO1 or LDO2 is configured as bypass, it allows voltage and function changes between LDO (VOUT=1.8V) and VOUT=VSET register setting. This voltage/function change can be triggered by hardware (using the VSEL_SD pin when configured as SD) or by software (VSEL_SD_I2C_CTRL).