SLVUCJ3 February   2023 TPS65220

 

  1.   ABSTRACT
  2.   Trademarks
  3. 1Introduction
  4. 2EEPROM Device Settings
    1. 2.1  Device ID
    2. 2.2  Enable Settings
    3. 2.3  Regulator Voltage Settings
    4. 2.4  Power Sequence Settings
      1. 2.4.1 Power Sequence Settings - Slot assignments
      2. 2.4.2 Power Sequence Settings - Slot Durations
      3. 2.4.3 TPS6522053 Sequence and Power Block Diagram
    5. 2.5  EN / PB / VSENSE Settings
    6. 2.6  Multi-Function Pin Settings
    7. 2.7  Over-Current Deglitch
    8. 2.8  Mask Settings
    9. 2.9  Discharge Check
    10. 2.10 Multi PMIC Config

2.7 Over-Current Deglitch

This section describes the default settings for the over current deglitch. When any of these registers are set (value = 1b), it enabled the long-deglitch option for the corresponding rail.

Table 2-14 Over Current Deglitch
Register Name Field Name Value Description
OC_DEGL_CONFIG EN_LONG_DEGL_FOR_OC_BUCK1 0x0 Deglitch duration for OverCurrent signals for BUCK1 (High-Side Overcurrent, Low-Side Overcurrent and Low-Side Reverse/Negative OverCurrent) is ~20us
OC_DEGL_CONFIG EN_LONG_DEGL_FOR_OC_BUCK2 0x0 Deglitch duration for OverCurrent signals for BUCK2 (High-Side Overcurrent, Low-Side Overcurrent and Low-Side Reverse/Negative OverCurrent) is ~20us
OC_DEGL_CONFIG EN_LONG_DEGL_FOR_OC_BUCK3 0x0 Deglitch duration for OverCurrent signals for BUCK3 (High-Side Overcurrent, Low-Side Overcurrent and Low-Side Reverse/Negative OverCurrent) is ~20us
OC_DEGL_CONFIG EN_LONG_DEGL_FOR_OC_LDO1 0x0 Deglitch duration for OverCurrent signals of LDO1 is ~20us
OC_DEGL_CONFIG EN_LONG_DEGL_FOR_OC_LDO2 0x0 Deglitch duration for OverCurrent signals of LDO2 is ~20us
OC_DEGL_CONFIG EN_LONG_DEGL_FOR_OC_LDO3 0x0 Deglitch duration for OverCurrent signals of LDO3 is ~20us
OC_DEGL_CONFIG EN_LONG_DEGL_FOR_OC_LDO4 0x0 Deglitch duration for OverCurrent signals of LDO4 is ~20us