SLVUCJ3 February   2023 TPS65220

 

  1.   ABSTRACT
  2.   Trademarks
  3. 1Introduction
  4. 2EEPROM Device Settings
    1. 2.1  Device ID
    2. 2.2  Enable Settings
    3. 2.3  Regulator Voltage Settings
    4. 2.4  Power Sequence Settings
      1. 2.4.1 Power Sequence Settings - Slot assignments
      2. 2.4.2 Power Sequence Settings - Slot Durations
      3. 2.4.3 TPS6522053 Sequence and Power Block Diagram
    5. 2.5  EN / PB / VSENSE Settings
    6. 2.6  Multi-Function Pin Settings
    7. 2.7  Over-Current Deglitch
    8. 2.8  Mask Settings
    9. 2.9  Discharge Check
    10. 2.10 Multi PMIC Config

2.8 Mask Settings

This section describes the settings that are masked by default and the effect they have on the device state as well as the nINT pin.

Table 2-15 Mask Settings
Register Name Field Name Value Description
Mask effects on device state and nINT pin MASK_CONFIG MASK_EFFECT 0x03 no state change, nINT reaction, bit set for Faults
UV Mask INT_MASK_UV BUCK1_UV_MASK 0x0 un-masked (Faults reported)
INT_MASK_UV BUCK2_UV_MASK 0x0 un-masked (Faults reported)
INT_MASK_UV BUCK3_UV_MASK 0x0 un-masked (Faults reported)
INT_MASK_UV LDO1_UV_MASK 0x0 un-masked (Faults reported)
INT_MASK_UV LDO2_UV_MASK 0x0 un-masked (Faults reported)
INT_MASK_UV LDO3_UV_MASK 0x0 un-masked (Faults reported)
INT_MASK_UV LDO4_UV_MASK 0x0 un-masked (Faults reported)
Power-up retries/attempts INT_MASK_UV MASK_RETRY_COUNT 0x0 Device does retry up to 2 times, then stay off
Die Temperature MASK_CONFIG SENSOR_0_WARM_MASK 0x0 un-masked (Faults reported)
MASK_CONFIG SENSOR_1_WARM_MASK 0x0 un-masked (Faults reported)
MASK_CONFIG SENSOR_2_WARM_MASK 0x0 un-masked (Faults reported)
MASK_CONFIG SENSOR_3_WARM_MASK 0x0 un-masked (Faults reported)
Masking bit to control whether nINT pin is sensitive to PushButton (PB) MASK_CONFIG MASK_INT_FOR_PB 0x1 masked (nINT not sensitive to any PB events)
Masking bit to control whether nINT pin is sensitive to RV (Residual Voltage) MASK_CONFIG MASK_INT_FOR_RV 0x0 un-masked (nINT pulled low for any RV events during transition to ACTIVE state or during enabling of rails)