SLVUCJ3 February   2023 TPS65220

 

  1.   ABSTRACT
  2.   Trademarks
  3. 1Introduction
  4. 2EEPROM Device Settings
    1. 2.1  Device ID
    2. 2.2  Enable Settings
    3. 2.3  Regulator Voltage Settings
    4. 2.4  Power Sequence Settings
      1. 2.4.1 Power Sequence Settings - Slot assignments
      2. 2.4.2 Power Sequence Settings - Slot Durations
      3. 2.4.3 TPS6522053 Sequence and Power Block Diagram
    5. 2.5  EN / PB / VSENSE Settings
    6. 2.6  Multi-Function Pin Settings
    7. 2.7  Over-Current Deglitch
    8. 2.8  Mask Settings
    9. 2.9  Discharge Check
    10. 2.10 Multi PMIC Config

2.5 EN / PB / VSENSE Settings

The EN/PB/VSENSE pin is used to enable or disable the PMIC. This pin can be configured in one of three ways: EN, PB or VSENSE. The table below shows the default configuration on for this TRM which is linked to a specific part number. Please note, if the FSD (First supply detection) feature is enabled, the device goes from "No Power" to "Active" state, executing the power-up sequence as soon as the voltage on VSYS is above the POR threshold. In this scenario, the EN/PB/VSENSE pin is ignored ONLY during the first power-up.

Table 2-10 EN / PB / VSENSE Settings
Register Name Field Name Value Description
MFP_2_CONFIG EN_PB_VSENSE_CONFIG 0x00 Device Enable Configuration
MFP_2_CONFIG EN_PB_VSENSE_DEGL 0x0 short (typ: 120us if configured as EN or VSENSE)
MFP_2_CONFIG PU_ON_FSD 0x1 First Supply Detection (FSD) Enabled.
Note: When EN/PB/VSENSE is configured as Enable, the deglitch time selected on "EN_PB_VSENSE_DEGL" is for the rising edge. Falling edge deglitch is not configurable. See data sheet for more details.