SLVUCF4 August   2022

PRODUCTION DATA  

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Default Board Configuration
    2. 1.2 Alternate Board Configurations
  4. 2EVM Connectors and Test Points
  5. 3Test Results
    1. 3.1 Parallel Configuration Results
  6. 4Load Transient Circuitry
  7. 5Board Layout
  8. 6Schematic
    1. 6.1 Parallel Configuration Schematic
    2. 6.2 Single Configuration Schematic
  9. 7Bill of Materials (BOM)
    1. 7.1 Parallel Configuration BOM
    2. 7.2 Single Configuration BOM
  10. 8Revision History
  11. 9Related Documentation

2 EVM Connectors and Test Points

GUID-20220802-SS0I-8JHL-G2JD-RLJ77PNRS3R9-low.png Figure 2-1 TPS7H2221EVM 3D Rendering (Top)
Table 2-1 Summary of Connectors and Test Points
Connector or Jumper

Test Point

Function
J1J5, TP1

VIN1

Input Power for Board

J8

J12, TP6

VIN2

J2J7, TP2

VOUT1

Output Power for Board

J9

J14, TP7

VOUT2

J3, J4, J10, J11

J17, J18, TP3, TP8

GND

Ground

J6, JP2

TP5

ON1

ON Pin

J13, JP7

TP10

ON2

JP3, JP4, JP5

TP4

QOD1QOD Pin

JP8, JP9, JP10

TP9

QOD2

J15TP11

TRANS

Output Transient FET Gate Signal

N/A

J16

I_SENSE

Output Transient Current Sense Test Point