SLVUCD2 January   2022 TPS65917-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2BOOT OTP Configuration
  4. 3Static Platform Settings
    1. 3.1 System Voltage Monitoring
    2. 3.2 SMPS
    3. 3.3 LDO
    4. 3.4 Interrupts
    5. 3.5 GPIO
    6. 3.6 MISC
    7. 3.7 SWOFF_HWRST
    8. 3.8 Shutdown_ColdReset
  5. 4Sequence Platform Settings
    1. 4.1 OFF2ACT Sequences
    2. 4.2 ACT2OFF Sequences

3.5 GPIO

TPS65917-Q1 integrates eight configurable general-purpose I/Os (GPIOs) that are multiplexed with alternative features. This section describes the default configuration of each GPIO, as well as the configuration of internal pullup or pulldown resistors on the GPIOs.

Table 3-8 GPIO Function OTP Settings
REGISTERBITDESCRIPTIONOTP VALUE
PRIMARY_SECONDARY_PAD2GPIO_6Select pin functionREGEN3
GPIO_5Select pin functionPOWERHOLD
GPIO_4Select pin functionREGEN2
PRIMARY_SECONDARY_PAD1GPIO_3Select pin functionSYNCDCDC
GPIO_2Select pin functionGPIO_2
GPIO_1Select pin functionRESET_IN
GPIO_0Select pin functionREGEN1
Note:

The GPIO_0 pin is an open drain pin and therefore must be pulled up externally. TI does not recommend pulling the GPIO_0 pin up to any always-on signal such as VCCA or LDOVRTC_OUT. The GPIO_0 pin is configured as an input before the OTP memory is loaded at power up, and pulling the pin up to an always-on rail can cause a glitch on the GPIO_0 pin. Therefore, TI recommends pulling this signal up to a sequenced output, such as SMPS3 (1.8 V) or LDO4 (3.3 V).

Table 3-9 describes the pullup, pulldown, and open-drain settings for the corresponding GPIOs. These settings only apply in GPIO mode (example: GPIO_0), and do not apply to any of the secondary functions (example: REGEN1).

Table 3-9 GPIO Pullup, Pulldown, and Open Drain Settings
REGISTERBITDESCRIPTIONOTP VALUE
PU_PD_GPIO_CTRL2GPIO_6_PDConfigure pulldown for GPIO_60: Pulldown disabled
GPIO_5_PDConfigure pulldown for GPIO_50: Pulldown disabled
GPIO_4_PUConfigure pullup for GPIO_40: Pullup disabled
GPIO_4_PDConfigure pulldown for GPIO_40: Pulldown disabled
PU_PD_GPIO_CTRL1GPIO_3_PDConfigure pulldown for GPIO_30: Pulldown disabled
GPIO_2_PUConfigure pullup for GPIO_20: Pullup disabled
GPIO_2_PDConfigure pulldown for GPIO_20: Pulldown disabled
GPIO_1_PDConfigure pulldown for GPIO_10: Pulldown disabled
GPIO_0_PDConfigure pulldown for GPIO_00: Pulldown disabled
OD_OUTPUT_GPIOGPIO_4_ODConfigure GPIO_4 to be open-drain or push-pull1: Open-drain
GPIO_2_ODConfigure GPIO_2 to be open-drain or push-pull0: Push-pull

Table 3-10 describes the polarity settings for each GPIO. These settings apply to both GPIO mode and secondary functions.

Table 3-10 GPIO Polarity Settings
REGISTERBITDESCRIPTIONOTP VALUE
POLARITY_CTRLGPIO_6_POLARITYEnable or disable polarity inversion for GPIO_60: Inversion disabled
GPIO_5_POLARITYEnable or disable polarity inversion for GPIO_50: Inversion disabled
GPIO_4_POLARITYEnable or disable polarity inversion for GPIO_40: Inversion disabled
GPIO_3_POLARITYEnable or disable polarity inversion for GPIO_30: Inversion disabled
GPIO_2_POLARITYEnable or disable polarity inversion for GPIO_20: Inversion disabled
GPIO_1_POLARITYEnable or disable polarity inversion for GPIO_11: Inversion enabled
GPIO_0_POLARITYEnable or disable polarity inversion for GPIO_00: Inversion disabled