SLVUC11 April   2021 DP83561-SP

 

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3.2.1 Bootstrap Options

Some DP83561-SP configurations can be done through bootstrap options. Options can be selected with jumpers or resistor population. Refer to the device data sheet for additional information on bootstrap options. Refer to the schematic and layout sections of this User’s Guide for resistor and jumper locations. By default, PHY address must be set to 00 and all straps must be mode 0 except for MIRROR_EN.

Table 3-2 DP83561-SP 4-Level Bootstrap Resistor Designation and Suggested Bootstrap Resistor Values
PIN NAME PIN NUMBER STRAP NAME STRAP MODE PU RESISTOR (KΩ) PU RESISTOR DESIGNATION PD RESISTOR (KΩ) PD RESISTOR DESIGNATION
RX_D0 44 PHY_ADD[1:0] 1 OPEN R152 OPEN R154
2 10 2.49
3 5.76 2.49
4 2.49 OPEN
RX_D1 45 PHY_ADD[3:2] 1 OPEN R155 OPEN R158
2 10 2.49
3 5.76 2.49
4 2.49 OPEN
Table 3-3 DP83561-SP 2-Level Bootstrap Selection and Jumper Designation
PIN NAME PIN NUMBER STRAP NAME STRAP MODE JUMPER PLACEMENT JUMPER DESIGNATION
VDDIOSEL_0 22 VDDIOSEL_0 0 OPEN J36
1 CLOSED
VDDIOSEL_1 21 VDDIOSEL_1 0 OPEN J35
1 CLOSED
SUPPLYMODE_SEL 23 SUPPLYMODE_SEL 0 OPEN J37
1 CLOSED
CRS/GPIO_3 33 RGMII/MII_SEL 0 OPEN J41
1 CLOSED
AUTO_RECOVER 34 AUTO_RECOVER 0 OPEN J39
1 CLOSED
RX_CTRL 48 MIRROR_EN 0 OPEN J31
1 CLOSED
SMI_DISABLE 50 SMI_DISABLE 0 OPEN J40
1 CLOSED
POWERGOOD 59 POWERGOOD 0 OPEN N/A
1 CLOSED
Table 3-4 DP83561-SP LED Bootstrap Selection and Jumper Designation
PIN NAME PIN NUMBER STRAP NAME STRAP MODE JUMPER PLACEMENT JUMPER DESIGNATION
LED_0 63 ANED_DIS 0 OPEN/PD J28
1 PU
LED_1 62 ANEGSEL_0 0 OPEN/PD J33
1 PU
LED_2 45 ANEGSEL_1 0 OPEN/PD J38
1 PU