SLVUBZ6 August   2020  – MONTH 

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Related Documentation
  3. 2Schematics, Bill of Materials, and Layout
    1. 2.1 TPS37AQ1EVM Schematic
    2. 2.2 TPS37AQ1EVM Bill of Materials
    3. 2.3 Layout and Component Placement
  4. 3EVM Connectors
    1. 3.1 EVM Test Points
    2. 3.2 EVM Jumpers
  5. 4EVM Setup and Operation
    1. 4.1 Input Power (VDD)
    2. 4.2 SENSE1/SENSE2 Inputs
    3. 4.3 RESET1/RESET2 Outputs
    4. 4.4 Capacitor Time Delay Reset/MR
    5. 4.5 Capacitor Time Delay Sense/MR

4.5 Capacitor Time Delay Sense/MR

The TPS37x-Q1 and TPS38x-Q1 family of devices contain two adjustable sense time delay pins that control the time with which the reset pins assert after they reach their invalid condition. The user can adjust the configuration of these pins via the jumpers located at J10 and J7. Header J10 serves as the selectable option for CTS1 and header J7 serves as the selectable option for CTS2. Position 1 of the header (located next to capacitor C7) connects the pin to a 1 µF capacitor tied to ground. Position 2 of the header (located next to capacitor C5) connects the pin to a 0.01 µF capacitor tied to ground. Position 3 of the header (located next to capacitor C4) connects the pin to a 0.033 µF capacitor tied to ground. Position 4 of the header (located next to capacitor pad C2) connects the pin to a unstuffed 0603 capacitor pad tied to ground which allows the user to solder on a capacitor of their choosing. Please see the Time Delay Configuration section on the TPS37x-Q1 datasheet for more detailed information on user programming.